[PATCH v3 07/11] dt-bindings: phy: renesas, usb2-phy: Document RZ/G2L phy bindings

[PATCH v3 07/11] dt-bindings: phy: renesas, usb2-phy: Document RZ/G2L phy bindings

[Biju Das]

Document USB phy bindings for RZ/G2L SoC.

RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
from this it uses a different OTG-BC interrupt bit for device recognition.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
 * Created a new compatible for RZ/G2L as per Geert's suggestion.
 * Added resets required properties for RZ/G2L SoC.
---
 .../bindings/phy/renesas,usb2-phy.yaml         | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index d5dc5a3cdceb..a7e585ff28dc 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -30,6 +30,9 @@ properties:
               - renesas,usb2-phy-r8a77995 # R-Car D3
           - const: renesas,rcar-gen3-usb2-phy
 
+      - items:
+          - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
+
   reg:
     maxItems: 1
 
@@ -91,6 +94,21 @@ required:
   - clocks
   - '#phy-cells'
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,usb2-phy-r9a07g044
+    then:
+      properties:
+        resets:
+          items:
+            - description: USB phy reset
+            - description: reset of USB 2.0 host side
+      required:
+        - resets
+
 additionalProperties: false
 
 examples:
-- 
2.17.1


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Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
> from this it uses a different OTG-BC interrupt bit for device recognition.

Nothing about resets? But see below...

>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
>  * Created a new compatible for RZ/G2L as per Geert's suggestion.
>  * Added resets required properties for RZ/G2L SoC.
> ---
>  .../bindings/phy/renesas,usb2-phy.yaml         | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index d5dc5a3cdceb..a7e585ff28dc 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -30,6 +30,9 @@ properties:
>                - renesas,usb2-phy-r8a77995 # R-Car D3
>            - const: renesas,rcar-gen3-usb2-phy
>
> +      - items:
> +          - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> +
>    reg:
>      maxItems: 1
>
> @@ -91,6 +94,21 @@ required:
>    - clocks
>    - '#phy-cells'
>
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,usb2-phy-r9a07g044
> +    then:
> +      properties:
> +        resets:
> +          items:
> +            - description: USB phy reset
> +            - description: reset of USB 2.0 host side

Do you need the second reset?
Looking at your .dtsi patch, the second reset is shared with ehci/ohci,
so perhaps it makes sense to drop it from the phy node?

> +      required:
> +        - resets
> +
>  additionalProperties: false
>
>  examples:

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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RE: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Document USB phy bindings for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes.
> > Apart from this it uses a different OTG-BC interrupt bit for device
> recognition.
> 
> Nothing about resets? But see below...

Initially the reset of USB/PHY port is in asserted state. So we need
to perform a release reset using USBPHY control IP. 

OK, will add this in V4.

> 
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> >  * Created a new compatible for RZ/G2L as per Geert's suggestion.
> >  * Added resets required properties for RZ/G2L SoC.
> > ---
> >  .../bindings/phy/renesas,usb2-phy.yaml         | 18 ++++++++++++++++++
> >  1 file changed, 18 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > index d5dc5a3cdceb..a7e585ff28dc 100644
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > @@ -30,6 +30,9 @@ properties:
> >                - renesas,usb2-phy-r8a77995 # R-Car D3
> >            - const: renesas,rcar-gen3-usb2-phy
> >
> > +      - items:
> > +          - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > +
> >    reg:
> >      maxItems: 1
> >
> > @@ -91,6 +94,21 @@ required:
> >    - clocks
> >    - '#phy-cells'
> >
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,usb2-phy-r9a07g044
> > +    then:
> > +      properties:
> > +        resets:
> > +          items:
> > +            - description: USB phy reset
> > +            - description: reset of USB 2.0 host side
> 
> Do you need the second reset?
> Looking at your .dtsi patch, the second reset is shared with ehci/ohci, so
> perhaps it makes sense to drop it from the phy node?

OK. Agreed will drop the second reset from phy node.

Cheers,
Biju

> 
> > +      required:
> > +        - resets
> > +
> >  additionalProperties: false
> >
> >  examples:
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds
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Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings

[Rob Herring]

On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote:
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Document USB phy bindings for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
> > from this it uses a different OTG-BC interrupt bit for device recognition.
> 
> Nothing about resets? But see below...
> 
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> >  * Created a new compatible for RZ/G2L as per Geert's suggestion.
> >  * Added resets required properties for RZ/G2L SoC.
> > ---
> >  .../bindings/phy/renesas,usb2-phy.yaml         | 18 ++++++++++++++++++
> >  1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > index d5dc5a3cdceb..a7e585ff28dc 100644
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > @@ -30,6 +30,9 @@ properties:
> >                - renesas,usb2-phy-r8a77995 # R-Car D3
> >            - const: renesas,rcar-gen3-usb2-phy
> >
> > +      - items:
> > +          - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > +
> >    reg:
> >      maxItems: 1
> >
> > @@ -91,6 +94,21 @@ required:
> >    - clocks
> >    - '#phy-cells'
> >
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,usb2-phy-r9a07g044
> > +    then:
> > +      properties:
> > +        resets:
> > +          items:
> > +            - description: USB phy reset
> > +            - description: reset of USB 2.0 host side
> 
> Do you need the second reset?
> Looking at your .dtsi patch, the second reset is shared with ehci/ohci,
> so perhaps it makes sense to drop it from the phy node?

The existing binding has the host reset (and peripheral, but no phy 
reset). Was that a mistake too? Smells like collecting resources the 
driver happens to want, not what the h/w connections are.

Rob

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RE: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings

[Biju Das]

Hi Rob,

> -----Original Message-----
> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
> 
> On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote:
> > Hi Biju,
> >
> > Thanks for your patch!
> >
> > On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Document USB phy bindings for RZ/G2L SoC.
> > >
> > > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes.
> > > Apart from this it uses a different OTG-BC interrupt bit for device
> recognition.
> >
> > Nothing about resets? But see below...
> >
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > >  * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > >  * Added resets required properties for RZ/G2L SoC.
> > > ---
> > >  .../bindings/phy/renesas,usb2-phy.yaml         | 18
> ++++++++++++++++++
> > >  1 file changed, 18 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > index d5dc5a3cdceb..a7e585ff28dc 100644
> > > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > @@ -30,6 +30,9 @@ properties:
> > >                - renesas,usb2-phy-r8a77995 # R-Car D3
> > >            - const: renesas,rcar-gen3-usb2-phy
> > >
> > > +      - items:
> > > +          - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > > +
> > >    reg:
> > >      maxItems: 1
> > >
> > > @@ -91,6 +94,21 @@ required:
> > >    - clocks
> > >    - '#phy-cells'
> > >
> > > +allOf:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            const: renesas,usb2-phy-r9a07g044
> > > +    then:
> > > +      properties:
> > > +        resets:
> > > +          items:
> > > +            - description: USB phy reset
> > > +            - description: reset of USB 2.0 host side
> >
> > Do you need the second reset?
> > Looking at your .dtsi patch, the second reset is shared with
> > ehci/ohci, so perhaps it makes sense to drop it from the phy node?
> 
> The existing binding has the host reset (and peripheral, but no phy
> reset). Was that a mistake too? Smells like collecting resources the
> driver happens to want, not what the h/w connections are.

On that SoC's there is no USBPHY control IP to control the reset. But PHY
is part of either host block or peripheral block. On RZ/G2L as well PHY is
part of Host block but we have dedicated IP to control the reset.

Regards,
Biju


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[PATCH v3 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L

[Biju Das]

This patch adds OTG support for RZ/G2L SoC.

We need to use a different compatible string due to some differences
with R-Car Gen3 USB2.0 PHY. It uses line ctrl register for OTG_ID
pin changes and different OTG-BC interrupt bit for device recognition.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 v3:
  * Made seperate compativle for RZ/G2L.
  * Extended rcar_gen3_phy_usb2_match_table[].data to support RZ/G2L.
---
 drivers/phy/renesas/phy-rcar-gen3-usb2.c | 97 ++++++++++++++++++------
 1 file changed, 73 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index fbc55232120e..ce875188b8cf 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -64,6 +64,7 @@
 /* VBCTRL */
 #define USB2_VBCTRL_OCCLREN		BIT(16)
 #define USB2_VBCTRL_DRVVBUSSEL		BIT(8)
+#define USB2_VBCTRL_VBOUT		BIT(0)
 
 /* LINECTRL1 */
 #define USB2_LINECTRL1_DPRPD_EN		BIT(19)
@@ -78,6 +79,10 @@
 #define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
 #define USB2_ADPCTRL_DRVVBUS		BIT(4)
 
+/*  RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN		BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON	BIT(0)
+
 #define NUM_OF_PHYS			4
 enum rcar_gen3_phy_index {
 	PHY_INDEX_BOTH_HC,
@@ -112,9 +117,16 @@ struct rcar_gen3_chan {
 	struct mutex lock;	/* protects rphys[...].powered */
 	enum usb_dr_mode dr_mode;
 	int irq;
+	u32 obint_enable_bits;
 	bool extcon_host;
 	bool is_otg_channel;
 	bool uses_otg_pins;
+	bool soc_no_adp_ctrl;
+};
+
+struct rcar_gen3_phy_drv_data {
+	const struct phy_ops *phy_usb2_ops;
+	bool no_adp_ctrl;
 };
 
 /*
@@ -172,14 +184,22 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
 static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
 {
 	void __iomem *usb2_base = ch->base;
-	u32 val = readl(usb2_base + USB2_ADPCTRL);
+	u32 vbus_ctrl_reg = USB2_ADPCTRL;
+	u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
+	u32 val;
 
 	dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
+	if (ch->soc_no_adp_ctrl) {
+		vbus_ctrl_reg = USB2_VBCTRL;
+		vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+	}
+
+	val = readl(usb2_base + vbus_ctrl_reg);
 	if (vbus)
-		val |= USB2_ADPCTRL_DRVVBUS;
+		val |= vbus_ctrl_val;
 	else
-		val &= ~USB2_ADPCTRL_DRVVBUS;
-	writel(val, usb2_base + USB2_ADPCTRL);
+		val &= ~vbus_ctrl_val;
+	writel(val, usb2_base + vbus_ctrl_reg);
 }
 
 static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
@@ -188,9 +208,9 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
 	u32 val = readl(usb2_base + USB2_OBINTEN);
 
 	if (ch->uses_otg_pins && enable)
-		val |= USB2_OBINT_BITS;
+		val |= ch->obint_enable_bits;
 	else
-		val &= ~USB2_OBINT_BITS;
+		val &= ~ch->obint_enable_bits;
 	writel(val, usb2_base + USB2_OBINTEN);
 }
 
@@ -252,6 +272,9 @@ static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
 	if (!ch->uses_otg_pins)
 		return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
 
+	if (ch->soc_no_adp_ctrl)
+		return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
+
 	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
 }
 
@@ -376,16 +399,17 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
 	      USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
 	writel(val, usb2_base + USB2_LINECTRL1);
 
-	val = readl(usb2_base + USB2_VBCTRL);
-	val &= ~USB2_VBCTRL_OCCLREN;
-	writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
-	val = readl(usb2_base + USB2_ADPCTRL);
-	writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
-
+	if (!ch->soc_no_adp_ctrl) {
+		val = readl(usb2_base + USB2_VBCTRL);
+		val &= ~USB2_VBCTRL_OCCLREN;
+		writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
+		val = readl(usb2_base + USB2_ADPCTRL);
+		writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
+	}
 	msleep(20);
 
 	writel(0xffffffff, usb2_base + USB2_OBINTSTA);
-	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
+	writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
 
 	rcar_gen3_device_recognition(ch);
 }
@@ -397,9 +421,9 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
 	u32 status = readl(usb2_base + USB2_OBINTSTA);
 	irqreturn_t ret = IRQ_NONE;
 
-	if (status & USB2_OBINT_BITS) {
+	if (status & ch->obint_enable_bits) {
 		dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
-		writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
+		writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
 		rcar_gen3_device_recognition(ch);
 		ret = IRQ_HANDLED;
 	}
@@ -535,26 +559,45 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
+	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+	.no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
+	.phy_usb2_ops = &rz_g1c_phy_usb2_ops,
+	.no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
+	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+	.no_adp_ctrl = true,
+};
+
 static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
 	{
 		.compatible = "renesas,usb2-phy-r8a77470",
-		.data = &rz_g1c_phy_usb2_ops,
+		.data = &rz_g1c_phy_usb2_data,
 	},
 	{
 		.compatible = "renesas,usb2-phy-r8a7795",
-		.data = &rcar_gen3_phy_usb2_ops,
+		.data = &rcar_gen3_phy_usb2_data,
 	},
 	{
 		.compatible = "renesas,usb2-phy-r8a7796",
-		.data = &rcar_gen3_phy_usb2_ops,
+		.data = &rcar_gen3_phy_usb2_data,
 	},
 	{
 		.compatible = "renesas,usb2-phy-r8a77965",
-		.data = &rcar_gen3_phy_usb2_ops,
+		.data = &rcar_gen3_phy_usb2_data,
+	},
+	{
+		.compatible = "renesas,usb2-phy-r9a07g044",
+		.data = &rz_g2l_phy_usb2_data,
 	},
 	{
 		.compatible = "renesas,rcar-gen3-usb2-phy",
-		.data = &rcar_gen3_phy_usb2_ops,
+		.data = &rcar_gen3_phy_usb2_data,
 	},
 	{ /* sentinel */ },
 };
@@ -608,10 +651,10 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
 
 static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 {
+	const struct rcar_gen3_phy_drv_data *phy_data;
 	struct device *dev = &pdev->dev;
 	struct rcar_gen3_chan *channel;
 	struct phy_provider *provider;
-	const struct phy_ops *phy_usb2_ops;
 	int ret = 0, i;
 
 	if (!dev->of_node) {
@@ -627,6 +670,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 	if (IS_ERR(channel->base))
 		return PTR_ERR(channel->base);
 
+	channel->obint_enable_bits = USB2_OBINT_BITS;
 	/* get irq number here and request_irq for OTG in phy_init */
 	channel->irq = platform_get_irq_optional(pdev, 0);
 	channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
@@ -653,16 +697,21 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
 	 * And then, phy-core will manage runtime pm for this device.
 	 */
 	pm_runtime_enable(dev);
-	phy_usb2_ops = of_device_get_match_data(dev);
-	if (!phy_usb2_ops) {
+
+	phy_data = of_device_get_match_data(dev);
+	if (!phy_data) {
 		ret = -EINVAL;
 		goto error;
 	}
 
+	channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl;
+	if (phy_data->no_adp_ctrl)
+		channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+
 	mutex_init(&channel->lock);
 	for (i = 0; i < NUM_OF_PHYS; i++) {
 		channel->rphys[i].phy = devm_phy_create(dev, NULL,
-							phy_usb2_ops);
+							phy_data->phy_usb2_ops);
 		if (IS_ERR(channel->rphys[i].phy)) {
 			dev_err(dev, "Failed to create USB2 PHY\n");
 			ret = PTR_ERR(channel->rphys[i].phy);
-- 
2.17.1


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