From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <a-govindraju@ti.com>
Subject: [PATCH v4 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
Date: Thu, 23 Dec 2021 07:01:36 +0100 [thread overview]
Message-ID: <20211223060137.9252-15-sjakhade@cadence.com> (raw)
In-Reply-To: <20211223060137.9252-1-sjakhade@cadence.com>
Add clock ID for Sierra derived reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
---
include/dt-bindings/phy/phy-cadence.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index d55fe6e6b936..0671991208fc 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -18,5 +18,6 @@
/* Sierra */
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
+#define CDNS_SIERRA_DERIVED_REFCLK 2
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */
--
2.26.1
--
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next prev parent reply other threads:[~2021-12-23 6:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-23 6:01 [PATCH v4 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-12-23 6:01 ` [PATCH v4 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-12-23 6:01 ` Swapnil Jakhade [this message]
2021-12-23 6:01 ` [PATCH v4 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
2021-12-27 11:07 ` [PATCH v4 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Vinod Koul
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