From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <robh+dt@kernel.org>, <lee.jones@linaro.org>,
<krzysztof.kozlowski@linaro.org>,
<krzysztof.kozlowski+dt@linaro.org>, <kishon@ti.com>,
<vkoul@kernel.org>, <dan.carpenter@oracle.com>,
<grygorii.strashko@ti.com>, <rogerq@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>, <s-vadapalli@ti.com>
Subject: [PATCH v5 2/3] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200
Date: Mon, 12 Sep 2022 14:26:49 +0530 [thread overview]
Message-ID: <20220912085650.83263-3-s-vadapalli@ti.com> (raw)
In-Reply-To: <20220912085650.83263-1-s-vadapalli@ti.com>
TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
.../mfd/ti,j721e-system-controller.yaml | 6 +++++
.../bindings/phy/ti,phy-gmii-sel.yaml | 25 +++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 1aeac43cad92..873ee0c0973f 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -54,6 +54,12 @@ patternProperties:
description:
Clock provider for TI EHRPWM nodes.
+ "phy@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
+ description:
+ The phy node corresponding to the ethernet MAC.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index 016a37db1ea1..da7cac537e15 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -53,12 +53,25 @@ properties:
- ti,am43xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
+ - ti,j7200-cpsw5g-phy-gmii-sel
reg:
maxItems: 1
'#phy-cells': true
+ ti,qsgmii-main-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Required only for QSGMII mode. Array to select the port for
+ QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
+ ports automatically. Any one of the 4 CPSW5G ports can act as the
+ main port with the rest of them being the QSGMII_SUB ports.
+ maxItems: 1
+ items:
+ minimum: 1
+ maximum: 4
+
allOf:
- if:
properties:
@@ -73,6 +86,18 @@ allOf:
'#phy-cells':
const: 1
description: CPSW port number (starting from 1)
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,j7200-cpsw5g-phy-gmii-sel
+ then:
+ properties:
+ ti,qsgmii-main-ports: false
+
- if:
properties:
compatible:
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-09-12 8:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-12 8:56 [PATCH v5 0/3] Add support for QSGMII mode Siddharth Vadapalli
2022-09-12 8:56 ` [PATCH v5 1/3] dt-bindings: phy: ti: phy-gmii-sel: Cleanup example Siddharth Vadapalli
2022-09-13 9:23 ` Krzysztof Kozlowski
2022-09-12 8:56 ` Siddharth Vadapalli [this message]
2022-09-13 9:27 ` [PATCH v5 2/3] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200 Krzysztof Kozlowski
2022-09-13 9:45 ` Siddharth Vadapalli
2022-09-13 10:17 ` Krzysztof Kozlowski
2022-09-12 8:56 ` [PATCH v5 3/3] phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200 Siddharth Vadapalli
2022-09-13 17:40 ` [PATCH v5 0/3] Add support for QSGMII mode Vinod Koul
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