[PATCH v3 08/13] phy: qcom-qmp-ufs: rename regs layout arrays

Dmitry Baryshkov
2022-11-10T19:32:41Z

Rename regs layouts to follow the QMP PHY version.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 4 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 ++++++++++---------
2 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
index bcca23493b7e..43255e8bf038 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
@@ -8,6 +8,9 @@
#define QCOM_PHY_QMP_PCS_UFS_V5_H_

/* Only for QMP V5 PHY - UFS PCS registers */
+#define QPHY_V5_PCS_UFS_PHY_START 0x000
+#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V5_PCS_UFS_SW_RESET 0x008
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
@@ -21,6 +24,7 @@
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
+#define QPHY_V5_PCS_UFS_READY_STATUS 0x180
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 8a7a3bfbd8d3..c9698e17b617 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -71,31 +71,32 @@ enum qphy_reg_layout {
QPHY_LAYOUT_SIZE
};

-static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
};

-static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
};

-static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
- [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
- [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
-};
-
-static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
+static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
};

+static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
+ [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
+ [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
+};
+
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
@@ -647,7 +648,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),

- .regs = msm8996_ufsphy_regs_layout,
+ .regs = ufsphy_v2_regs_layout,

.no_pcs_sw_reset = true,
};
@@ -669,7 +670,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8150_ufsphy_regs_layout,
+ .regs = ufsphy_v5_regs_layout,
};

static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
@@ -687,7 +688,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sdm845_ufsphy_regs_layout,
+ .regs = ufsphy_v3_regs_layout,

.no_pcs_sw_reset = true,
};
@@ -707,7 +708,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm6115_ufsphy_regs_layout,
+ .regs = ufsphy_v2_regs_layout,

.no_pcs_sw_reset = true,
};
@@ -727,7 +728,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8150_ufsphy_regs_layout,
+ .regs = ufsphy_v4_regs_layout,
};

static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
@@ -745,7 +746,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8150_ufsphy_regs_layout,
+ .regs = ufsphy_v5_regs_layout,
};

static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
@@ -763,7 +764,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8150_ufsphy_regs_layout,
+ .regs = ufsphy_v5_regs_layout,
};

static void qmp_ufs_configure_lane(void __iomem *base,