From: Chintan Vankar <c-vankar@ti.com>
To: "Maxime Ripard" <mripard@kernel.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Sinthu Raja" <sinthu.raja@ti.com>,
"Chintan Vankar" <c-vankar@ti.com>, "Andrew Davis" <afd@ti.com>,
"Siddharth Vadapalli" <s-vadapalli@ti.com>,
"Roger Quadros" <rogerq@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>
Subject: [RFC PATCH 1/2] phy: ti: gmii-sel: Enable SGMII mode for J784S4
Date: Thu, 21 Dec 2023 15:59:55 +0530 [thread overview]
Message-ID: <20231221102956.754617-1-c-vankar@ti.com> (raw)
TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
drivers/phy/ti/phy-gmii-sel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index bc847d3879f7..0f4818adb440 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -248,7 +248,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
BIT(PHY_INTERFACE_MODE_USXGMII),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
--
2.34.1
--
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next reply other threads:[~2023-12-21 10:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 10:29 Chintan Vankar [this message]
2023-12-21 10:29 ` [RFC PATCH 2/2] phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 Chintan Vankar
2023-12-22 10:13 ` Roger Quadros
2023-12-22 10:12 ` [RFC PATCH 1/2] phy: ti: gmii-sel: Enable SGMII mode " Roger Quadros
2023-12-22 15:50 ` Vinod Koul
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