From: kernel test robot <lkp@intel.com>
To: "André Draszik" <andre.draszik@linaro.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Peter Griffin" <peter.griffin@linaro.org>,
"Marek Szyprowski" <m.szyprowski@samsung.com>,
"Sylwester Nawrocki" <s.nawrocki@samsung.com>,
"Alim Akhtar" <alim.akhtar@samsung.com>,
"Sam Protsenko" <semen.protsenko@linaro.org>
Cc: oe-kbuild-all@lists.linux.dev,
"Tudor Ambarus" <tudor.ambarus@linaro.org>,
"Will McVicker" <willmcvicker@google.com>,
"Roy Luo" <royluo@google.com>,
kernel-team@android.com, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org,
"André Draszik" <andre.draszik@linaro.org>
Subject: Re: [PATCH 7/7] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
Date: Wed, 24 Apr 2024 13:55:01 +0800 [thread overview]
Message-ID: <202404241343.bJvpqJob-lkp@intel.com> (raw)
In-Reply-To: <20240423-usb-phy-gs101-v1-7-ebdcb3ac174d@linaro.org>
Hi André,
kernel test robot noticed the following build errors:
[auto build test ERROR on a59668a9397e7245b26e9be85d23f242ff757ae8]
url: https://github.com/intel-lab-lkp/linux/commits/Andr-Draszik/dt-bindings-phy-samsung-usb3-drd-phy-add-gs101-compatible/20240424-011137
base: a59668a9397e7245b26e9be85d23f242ff757ae8
patch link: https://lore.kernel.org/r/20240423-usb-phy-gs101-v1-7-ebdcb3ac174d%40linaro.org
patch subject: [PATCH 7/7] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
config: arc-randconfig-002-20240424 (https://download.01.org/0day-ci/archive/20240424/202404241343.bJvpqJob-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240424/202404241343.bJvpqJob-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404241343.bJvpqJob-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready':
drivers/phy/samsung/phy-exynos5-usbdrd.c:615:16: error: implicit declaration of function 'FIELD_PREP_CONST' [-Werror=implicit-function-declaration]
615 | reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1);
| ^~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynos850_usbdrd_utmi_init':
>> drivers/phy/samsung/phy-exynos5-usbdrd.c:1147:20: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
1147 | ss_ports = FIELD_GET(LINKPORT_HOST_NUM_U3, reg);
| ^~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c: At top level:
>> drivers/phy/samsung/phy-exynos5-usbdrd.c:302:24: error: initializer element is not constant
302 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1411:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PHY'
1411 | PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:302:24: note: (near initialization for 'gs101_tunes_utmi_postinit[0].val')
302 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1411:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PHY'
1411 | PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1483:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1483 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[3].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1483:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1483 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1487:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1487 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[4].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1487:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1487 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1493:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1493 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[5].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1493:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1493 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1504:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1504 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL_DEBUG,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[8].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1504:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1504 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL_DEBUG,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1514:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1514 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_HS_TX_COEF_MAP_0,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[9].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1514:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1514 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_HS_TX_COEF_MAP_0,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1521:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1521 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_LOCAL_COEF,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[10].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1521:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1521 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_LOCAL_COEF,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: error: initializer element is not constant
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1527:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1527 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_EBUF_PARAM,
| ^~~~~~~~~~~~~~~~~~~~
drivers/phy/samsung/phy-exynos5-usbdrd.c:309:24: note: (near initialization for 'gs101_tunes_pipe3_init[12].val')
309 | .val = (v), \
| ^
drivers/phy/samsung/phy-exynos5-usbdrd.c:1527:9: note: in expansion of macro 'PHY_TUNING_ENTRY_PCS'
1527 | PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_EBUF_PARAM,
| ^~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/FIELD_GET +1147 drivers/phy/samsung/phy-exynos5-usbdrd.c
1130
1131 static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
1132 {
1133 void __iomem *regs_base = phy_drd->reg_phy;
1134 u32 reg;
1135 u32 ss_ports;
1136
1137 /*
1138 * Disable HWACG (hardware auto clock gating control). This will force
1139 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
1140 * the PHY clock is not gated by the hardware.
1141 */
1142 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1143 reg |= LINKCTRL_FORCE_QACT;
1144 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
1145
1146 reg = readl(regs_base + EXYNOS850_DRD_LINKPORT);
> 1147 ss_ports = FIELD_GET(LINKPORT_HOST_NUM_U3, reg);
1148
1149 /* Start PHY Reset (POR=high) */
1150 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
1151 if (ss_ports) {
1152 reg |= CLKRST_PHY20_SW_POR;
1153 reg |= CLKRST_PHY20_SW_POR_SEL;
1154 reg |= CLKRST_PHY_RESET_SEL;
1155 }
1156 reg |= CLKRST_PHY_SW_RST;
1157 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1158
1159 /* Enable UTMI+ */
1160 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
1161 reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN |
1162 UTMI_DM_PULLDOWN);
1163 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
1164
1165 /* Set PHY clock and control HS PHY */
1166 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1167 reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN;
1168 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1169
1170 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */
1171 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1172 reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf);
1173 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
1174
1175 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
1176 reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID;
1177 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
1178
1179 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1180 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
1181 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1182
1183 reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
1184 reg &= ~SSPPLLCTL_FSEL;
1185 switch (phy_drd->extrefclk) {
1186 case EXYNOS5_FSEL_50MHZ:
1187 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
1188 break;
1189 case EXYNOS5_FSEL_26MHZ:
1190 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
1191 break;
1192 case EXYNOS5_FSEL_24MHZ:
1193 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
1194 break;
1195 case EXYNOS5_FSEL_20MHZ:
1196 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
1197 break;
1198 case EXYNOS5_FSEL_19MHZ2:
1199 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
1200 break;
1201 default:
1202 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
1203 phy_drd->extrefclk);
1204 break;
1205 }
1206 writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
1207
1208 /* Power up PHY analog blocks */
1209 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
1210 reg &= ~HSP_TEST_SIDDQ;
1211 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
1212
1213 /* Finish PHY reset (POR=low) */
1214 udelay(10); /* required before doing POR=low */
1215 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
1216 if (ss_ports) {
1217 reg |= CLKRST_PHY20_SW_POR_SEL;
1218 reg &= ~CLKRST_PHY20_SW_POR;
1219 }
1220 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);
1221 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1222 udelay(75); /* required after POR=low for guaranteed PHY clock */
1223
1224 /* Disable single ended signal out */
1225 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1226 reg &= ~HSP_FSV_OUT_EN;
1227 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1228
1229 if (ss_ports)
1230 exynos5_usbdrd_usb_v3p1_pipe_override(phy_drd);
1231
1232 if (phy_drd->drv_data->phy_tunes)
1233 exynos5_usbdrd_apply_phy_tunes(phy_drd,
1234 PTS_UTMI_POSTINIT);
1235 }
1236
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prev parent reply other threads:[~2024-04-24 5:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-23 17:06 [PATCH 0/7] USB31DRD phy support for Google Tensor gs101 (HS & SS) André Draszik
2024-04-23 17:06 ` [PATCH 1/7] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible André Draszik
2024-04-24 19:43 ` Rob Herring
2024-04-23 17:06 ` [PATCH 2/7] phy: exynos5-usbdrd: use exynos_get_pmu_regmap_by_phandle() for PMU regs André Draszik
2024-04-25 7:47 ` Krzysztof Kozlowski
2024-04-25 10:02 ` Peter Griffin
2024-04-25 10:16 ` Krzysztof Kozlowski
2024-04-23 17:06 ` [PATCH 3/7] phy: exynos5-usbdrd: support isolating HS and SS ports independently André Draszik
2024-04-23 17:06 ` [PATCH 4/7] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init() André Draszik
2024-04-24 5:03 ` kernel test robot
2024-04-24 7:41 ` kernel test robot
2024-04-23 17:06 ` [PATCH 5/7] phy: exynos5-usbdrd: uniform order of register bit macros André Draszik
2024-04-23 17:06 ` [PATCH 6/7] phy: exynos5-usbdrd: convert to clk_bulk for phy (register) access André Draszik
2024-04-23 17:06 ` [PATCH 7/7] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) André Draszik
2024-04-24 5:55 ` kernel test robot [this message]
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