From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Wenbin Yao <quic_wenbyao@quicinc.com>
Cc: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de,
dmitry.baryshkov@linaro.org, abel.vesa@linaro.org,
quic_qianyu@quicinc.com, neil.armstrong@linaro.org,
quic_devipriy@quicinc.com, konrad.dybcio@oss.qualcomm.com,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support
Date: Fri, 14 Mar 2025 20:20:35 +0530 [thread overview]
Message-ID: <20250314145035.h3nybvvko3ew37wl@thinkpad> (raw)
In-Reply-To: <20250226103600.1923047-3-quic_wenbyao@quicinc.com>
On Wed, Feb 26, 2025 at 06:36:00PM +0800, Wenbin Yao wrote:
> From: Qiang Yu <quic_qianyu@quicinc.com>
>
> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
> whole PHY (hardware and register), no_csr reset only resets PHY hardware
> but retains register values, which means PHY setting can be skipped during
> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
> after that.
>
> Hence, determine whether the PHY has been enabled in bootloader by
> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
> available, skip BCR reset and PHY register setting to establish the PCIe
> link with bootloader - programmed PHY settings.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
One nit below.
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++----
> 1 file changed, 59 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 219266125cf2..c3642d1807e4 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -2805,6 +2805,7 @@ struct qmp_pcie {
>
> const struct qmp_phy_cfg *cfg;
> bool tcsr_4ln_config;
> + bool skip_init;
>
> void __iomem *serdes;
> void __iomem *pcs;
> @@ -3976,18 +3977,38 @@ static int qmp_pcie_init(struct phy *phy)
> {
> struct qmp_pcie *qmp = phy_get_drvdata(phy);
> const struct qmp_phy_cfg *cfg = qmp->cfg;
> + void __iomem *pcs = qmp->pcs;
> + bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
> int ret;
>
> + qmp->skip_init = qmp->nocsr_reset && phy_initialized;
> + /*
> + * We need to check the existence of init sequences in two cases:
> + * 1. The PHY doesn't support no_csr reset.
> + * 2. The PHY supports no_csr reset but isn't initialized by bootloader.
> + * As we can't skip init in these two cases.
> + */
> + if (!qmp->skip_init && !cfg->tbls.serdes_num) {
> + dev_err(qmp->dev, "no init sequences are available\n");
"Init sequence not available\n"
> + return -EINVAL;
-ENODATA
- Mani
--
மணிவண்ணன் சதாசிவம்
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next prev parent reply other threads:[~2025-03-14 14:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 10:35 [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support Wenbin Yao
2025-02-26 10:35 ` [PATCH v5 1/2] phy: qcom: pcie: Determine has_nocsr_reset dynamically Wenbin Yao
2025-02-26 10:36 ` [PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support Wenbin Yao
2025-03-14 14:50 ` Manivannan Sadhasivam [this message]
2025-03-18 6:56 ` Wenbin Yao (Consultant)
2025-03-10 8:58 ` [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support Wenbin Yao (Consultant)
2025-03-10 19:59 ` Vinod Koul
2025-03-14 14:54 ` Manivannan Sadhasivam
2025-03-14 22:42 ` Konrad Dybcio
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