[PATCH 2/7] dt-bindings: phy: spacemit: add K1 PCIe/USB3 combo PHY

Ze Huang
2025-04-07T15:12:35Z

Introduce support for SpacemiT K1 PCIe/USB3 combo PHY controller.

PCIe portA and USB3 controller share this phy, only one of them can work
at any given application scenario.

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
.../bindings/phy/spacemit,k1-combphy.yaml | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..450157b65410b27129603ea1f3523776a1b0a75e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combphy.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spacemit K1 PCIe/USB3 PHY
+
+maintainers:
+ - Ze Huang <huangze@whut.edu.cn>
+
+description:
+ Combo PHY on SpacemiT K1 SoC.PCIe port A and USB3 controller share this
+ phy, only one of PCIe port A and USB3 port can work at any given application
+ scenario.
+
+properties:
+ compatible:
+ const: spacemit,k1-combphy
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: phy_ctrl
+ - const: phy_sel
+
+ resets:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - resets
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@c0b10000 {
+ compatible = "spacemit,k1-combphy";
+ reg = <0xc0b10000 0x800>,
+ <0xd4282910 0x400>;
+ reg-names = "phy_ctrl", "phy_sel";
+ resets = <&syscon_apmu 19>;
+ #phy-cells = <1>;
+ };

--
2.49.0