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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
To: "Yury Norov" <yury.norov@gmail.com>,
	"Rasmus Villemoes" <linux@rasmusvillemoes.dk>,
	"Jaehoon Chung" <jh80.chung@samsung.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Shreeya Patel" <shreeya.patel@collabora.com>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Andy Yan" <andy.yan@rock-chips.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Nicolas Frattaroli" <frattaroli.nicolas@gmail.com>,
	"Liam Girdwood" <lgirdwood@gmail.com>,
	"Mark Brown" <broonie@kernel.org>,
	"Jaroslav Kysela" <perex@perex.cz>,
	"Takashi Iwai" <tiwai@suse.com>,
	"Andrew Lunn" <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
	"Alexandre Torgue" <alexandre.torgue@foss.st.com>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Chanwoo Choi" <cw00.choi@samsung.com>,
	"MyungJoo Ham" <myungjoo.ham@samsung.com>,
	"Kyungmin Park" <kyungmin.park@samsung.com>,
	"Qin Jian" <qinjian@cqplus1.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Nathan Chancellor" <nathan@kernel.org>,
	"Nick Desaulniers" <nick.desaulniers+lkml@gmail.com>,
	"Bill Wendling" <morbo@google.com>,
	"Justin Stitt" <justinstitt@google.com>
Cc: kernel@collabora.com, linux-kernel@vger.kernel.org,
	 linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org,
	 dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org,
	 linux-sound@vger.kernel.org, netdev@vger.kernel.org,
	 linux-stm32@st-md-mailman.stormreply.com,
	linux-pci@vger.kernel.org,  linux-pm@vger.kernel.org,
	linux-clk@vger.kernel.org, llvm@lists.linux.dev,
	 Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Subject: [PATCH v2 01/20] bitmap: introduce hardware-specific bitfield operations
Date: Mon, 23 Jun 2025 18:05:29 +0200	[thread overview]
Message-ID: <20250623-byeword-update-v2-1-cf1fc08a2e1f@collabora.com> (raw)
In-Reply-To: <20250623-byeword-update-v2-0-cf1fc08a2e1f@collabora.com>

Hardware of various vendors, but very notably Rockchip, often uses
32-bit registers where the upper 16-bit half of the register is a
write-enable mask for the lower half.

This type of hardware setup allows for more granular concurrent register
write access.

Over the years, many drivers have hand-rolled their own version of this
macro, usually without any checks, often called something like
HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different
semantics between them.

Clearly there is a demand for such a macro, and thus the demand should
be satisfied in a common header file. As this is a convention that spans
across multiple vendors, and similar conventions may also have
cross-vendor adoption, it's best if it lives in a vendor-agnostic header
file that can be expanded over time.

Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and
FIELD_PREP_WM16_CONST. The latter is a version that can be used in
initializers, like FIELD_PREP_CONST.

Suggested-by: Yury Norov [NVIDIA] <yury.norov@gmail.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 MAINTAINERS                 |  1 +
 include/linux/hw_bitfield.h | 62 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 41f13ccef4c84dcb1762c166553a2dc35704f211..8d2cf600d5cd722b5b08e81b6b24338fdc044240 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4187,6 +4187,7 @@ F:	include/linux/bits.h
 F:	include/linux/cpumask.h
 F:	include/linux/cpumask_types.h
 F:	include/linux/find.h
+F:	include/linux/hw_bitfield.h
 F:	include/linux/nodemask.h
 F:	include/linux/nodemask_types.h
 F:	include/vdso/bits.h
diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h
new file mode 100644
index 0000000000000000000000000000000000000000..df202e167ce487122e4440962eacb2e44817ad9f
--- /dev/null
+++ b/include/linux/hw_bitfield.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025, Collabora Ltd.
+ */
+
+#ifndef _LINUX_HW_BITFIELD_H
+#define _LINUX_HW_BITFIELD_H
+
+#include <linux/bitfield.h>
+#include <linux/build_bug.h>
+#include <linux/limits.h>
+
+/**
+ * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to put in the field
+ *
+ * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the
+ * result with the mask shifted up by 16.
+ *
+ * This is useful for a common design of hardware registers where the upper
+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
+ * register, a bit in the lower half is only updated if the corresponding bit
+ * in the upper half is high.
+ */
+#define FIELD_PREP_WM16(_mask, _val)					     \
+	({								     \
+		typeof(_val) __val = _val;				     \
+		typeof(_mask) __mask = _mask;				     \
+		__BF_FIELD_CHECK(__mask, ((u16)0U), __val,		     \
+				 "HWORD_UPDATE: ");			     \
+		(((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
+		((__mask) << 16);					     \
+	})
+
+/**
+ * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in
+ *                           the upper half
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to put in the field
+ *
+ * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs
+ * the result with the mask shifted up by 16.
+ *
+ * This is useful for a common design of hardware registers where the upper
+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
+ * register, a bit in the lower half is only updated if the corresponding bit
+ * in the upper half is high.
+ *
+ * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore
+ * be used in initializers. Error checking is less comfortable for this
+ * version.
+ */
+#define FIELD_PREP_WM16_CONST(_mask, _val)				 \
+	(								 \
+		FIELD_PREP_CONST(_mask, _val) |				 \
+		(BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \
+		 ((_mask) << 16))					 \
+	)
+
+
+#endif /* _LINUX_HW_BITFIELD_H */

-- 
2.50.0


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  reply	other threads:[~2025-06-23 19:42 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-23 16:05 [PATCH v2 00/20] BYEWORD_UPDATE: unifying (most) HIWORD_UPDATE macros Nicolas Frattaroli
2025-06-23 16:05 ` Nicolas Frattaroli [this message]
2025-06-23 16:05 ` [PATCH v2 02/20] mmc: dw_mmc-rockchip: switch to FIELD_PREP_WM16 macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 03/20] soc: rockchip: grf: switch to FIELD_PREP_WM16_CONST macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 04/20] media: synopsys: hdmirx: replace macros with bitfield variants Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 05/20] drm/rockchip: lvds: switch to FIELD_PREP_WM16 macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 06/20] phy: rockchip-emmc: " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 07/20] drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 08/20] drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 09/20] phy: rockchip-samsung-dcphy: " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 10/20] drm/rockchip: dw_hdmi_qp: " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 11/20] drm/rockchip: inno-hdmi: " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 12/20] phy: rockchip-usb: " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 13/20] drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 14/20] ASoC: rockchip: i2s-tdm: switch to FIELD_PREP_WM16_CONST macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 15/20] net: stmmac: dwmac-rk: switch to FIELD_PREP_WM16 macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 16/20] PCI: rockchip: Switch to FIELD_PREP_WM16* macros Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 17/20] PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 18/20] PM / devfreq: rockchip-dfi: switch " Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 19/20] clk: sp7021: " Nicolas Frattaroli
     [not found]   ` <175340605069.3513.18204498860033427106@lazor>
2025-08-25  7:48     ` Nicolas Frattaroli
2025-06-23 16:05 ` [PATCH v2 20/20] phy: rockchip-pcie: " Nicolas Frattaroli

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