From: Abel Vesa <abel.vesa@linaro.org>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>
Cc: Johan Hovold <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Abel Vesa <abel.vesa@linaro.org>
Subject: [PATCH v3 2/4] phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count
Date: Thu, 11 Sep 2025 17:45:23 +0300 [thread overview]
Message-ID: <20250911-phy-qcom-edp-add-glymur-support-v3-2-1c8514313a16@linaro.org> (raw)
In-Reply-To: <20250911-phy-qcom-edp-add-glymur-support-v3-0-1c8514313a16@linaro.org>
On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx
registers. This hasn't been an issue so far on currently supported
platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9.
However, on the new upcoming Glymur platform, these are updated along
with the rest of the init sequence.
So update the size of the array holding the config to 13.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..7b642742412e63149442e4befeb095307ec38173 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -32,7 +32,7 @@
#define DP_PHY_PD_CTL 0x001c
#define DP_PHY_MODE 0x0020
-#define DP_AUX_CFG_SIZE 10
+#define DP_AUX_CFG_SIZE 13
#define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n)))
#define DP_PHY_AUX_INTERRUPT_MASK 0x0058
--
2.45.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2025-09-11 14:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-11 14:45 [PATCH v3 0/4] phy: qcom: edp: Add support for Glymur platform Abel Vesa
2025-09-11 14:45 ` [PATCH v3 1/4] dt-bindings: phy: Add DP PHY compatible for Glymur Abel Vesa
2025-09-15 20:51 ` Rob Herring (Arm)
2025-09-11 14:45 ` Abel Vesa [this message]
2025-09-11 15:04 ` [PATCH v3 2/4] phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count Konrad Dybcio
2025-09-11 14:45 ` [PATCH v3 3/4] phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsets Abel Vesa
2025-09-11 14:45 ` [PATCH v3 4/4] phy: qcom: edp: Add Glymur platform support Abel Vesa
2025-09-11 21:28 ` Alexey Klimov
2025-09-12 7:43 ` Abel Vesa
-- strict thread matches above, loose matches on Subject: below --
2025-10-14 10:02 [PATCH v3 0/4] phy: qcom: edp: Add support for Glymur platform Abel Vesa
2025-10-14 10:02 ` [PATCH v3 2/4] phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count Abel Vesa
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