Re: [PATCH 12/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet

Sjoerd Simons
2025-10-22T06:56:37Z

On Tue, 2025-10-21 at 22:40 +0200, Andrew Lunn wrote:
> On Tue, Oct 21, 2025 at 10:21:31PM +0200, Sjoerd Simons wrote:
> > On Fri, 2025-10-17 at 19:31 +0200, Andrew Lunn wrote:
> > > > +&mdio_bus {
> > > > + phy15: ethernet-phy@f {
> > > > + compatible = "ethernet-phy-id03a2.a411";
> > > > + reg = <0xf>;
> > > > + interrupt-parent = <&pio>;
> > > > + interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
> > >
> > > This is probably wrong. PHY interrupts are generally level, not edge.
> >
> > Sadly i can't find a datasheet for the PHY, so can't really validate that
> > easily.
>
> What PHY is it? Look at the .handle_interrupt function in the
> driver. If the hardware supports a single interrupt bit, it could in
> theory support edge. However, as soon as you have multiple bits, you
> need level, to avoid races where an interrupt happens while you are
> clearing other interrupts.

ethernet-phy-id03a2.a411 is Airoha EN8811H (air_en8811h driver). Handle
interrupt there seems to just be a general interrupt clear followed by a
`phy_trigger_machine`. It doesn't seem to read specific interrupt status.

Testing with IRQ_TYPE_LEVEL_LOW does seem to work as expected and results in
detecting 4 interrupts rather then just 1 with edges when enabling the
interface. However I'm not sure what can be concluded from that if anything :)..

I can stick a scope on the line in the coming days to see how the interrupt line
behaves if interrupts aren't cleared, which may clarify things.

--
Sjoerd Simons
Collabora