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Thu, 20 Nov 2025 09:36:58 -0800 (PST) Date: Thu, 20 Nov 2025 17:36:40 +0000 Mime-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAKhRH2kC/0XMQQ6CMBCF4auQWVvSmRYIrryHcYF1gCbAkKkaC eHuNm5cfsn/3g6JNXKCc7GD8jumKEtGfSogjN0ysImPbCBLFSK2Zh23uzfE1nVN8L4NHnK7Kvf x8/u53rJ7ldk8R+Xuv7bUEnrrqHTYVFSjQaOyTS+5DCLDxGWQGY7jC6IpaBWUAAAA X-Change-Id: 20251119-phyb4-2e03a7c449c4 X-Developer-Key: i=royluo@google.com; a=ed25519; pk=nTq1n8WcJActRWe1s8jdcy+TzpTK4a+IYRCIWvQfq5k= X-Developer-Signature: v=1; a=ed25519-sha256; t=1763660216; l=4218; i=royluo@google.com; s=20251120; h=from:subject:message-id; bh=gsS3QINB3jX+ZRH8cuZXIVubPgqbPwUz2dBtzJJwyyE=; b=nKBxDu+hW1XAB/2+eENQ1XLCEWJM6tfpn4cqNbVISMLXtgHyz7sPjnMNHE4OAdBgCN6L1aByZ J445SDv9iPMBRmpMMTiBvqjX3bFNGPFqA0kfKFU1NRWRm3lXqWi9Guj X-Mailer: b4 0.14.2 Message-ID: <20251120-phyb4-v6-0-b6694e1f0caf@google.com> Subject: [PATCH v6 0/2] Add Google Tensor SoC USB PHY support From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , "=?utf-8?q?Andr=C3=A9_Draszik?=" , Tudor Ambarus , Philipp Zabel Cc: Badhri Jagan Sridharan , Doug Anderson , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Joy Chakraborty , Naveen Kumar , Roy Luo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251120_093700_114500_392C09E0 X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This series introduces USB PHY support for the Google Tensor G5 SoC (codename: Laguna), a new generation of Google silicon first launched with Pixel 10 devices. The Tensor G5 represents a significant architectural overhaul compared to previous Tensor generations (e.g., gs101), which were based on Samsung Exynos IP. Although the G5 still utilizes Synopsys IP for the USB components, the custom top-level integration introduces a completely new design for clock, reset scheme, register interfaces and programming sequence, necessitating new drivers and device tree bindings. The USB subsystem on Tensor G5 integrates a Synopsys DWC3 USB 3.1 DRD-Single Port controller with hibernation support, and a custom PHY block comprising Synopsys eUSB2 and USB 3.2/DP combo PHYs. The controller support is sent as a separate patch series. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- Changes in v6: - Use "lga" as SoC name instead of "gs5" to align with Tensor G5 device tree https://lore.kernel.org/lkml/20251111192422.4180216-1-dianders@chromium.org - Add "usb2_core" to the reg property to define the MMIO space for the eUSB 2.0 PHY IP. - Rename "usb3_top" reg as "usbdp_top" and update the description to reflect its nature as a top-level wrapper and align with internal documentation. - Use syscon to access the "usb2_cfg" MMIO space. - Remove minItems for clocks and resets, making all listed clocks and resets (including USB3) mandatory. Link to v5: https://lore.kernel.org/linux-phy/20251029214032.3175261-1-royluo@google.com Changes in v5: - Add usb3 registers/clks/resets to binding as suggested by Krzysztof Kozlowski. This ensures completeness of the binding, though the driver has not yet ultilized the resources. The usb3 clks and resets are optional if usb2-only operation is desired, this is denoted by minItems and descriptions in the clocks and resets properties. Additionally, rename existing binding entries for consistency and to better differntiate between usb2 and usb3. - Move the description of the phy select to phy-cells in binding as suggested by Krzysztof Kozlowski. Link to v4: https://lore.kernel.org/linux-phy/20251017235159.2417576-1-royluo@google.com Changes in v4: - Separate controller and phy changes into two distinct patch series. - Remove usb2only mode configuration and the corresponding usb_top_cfg reg (moved to controller) - Add more descriptions to dp_top reg to indicate it's not DP specific. - Add u2phy_apb clk/reset Link to v3: https://lore.kernel.org/linux-usb/20251010201607.1190967-1-royluo@google.com Changes in v3: - Align binding file name with the compatible string - Simplify the compatible property in binding to a single const value. - Add descriptive comments and use item list in binding. - Rename binding entries for clarity and brevity. Link to v2: https://lore.kernel.org/linux-usb/20251008060000.3136021-1-royluo@google.com Changes in v2: - Reorder patches to present bindings first. - Update dt binding compatible strings to be SoC-specific (google,gs5-*). - Better describe the hardware in dt binding commit messages and descriptions. - Adjust PHY driver commit subjects to use correct prefixes ("phy:"). - Move PHY driver from a subdirectory to drivers/phy/. Link to v1: https://lore.kernel.org/linux-usb/20251006232125.1833979-1-royluo@google.com/ --- Roy Luo (2): dt-bindings: phy: google: Add Google Tensor G5 USB PHY phy: Add Google Tensor SoC USB PHY driver .../bindings/phy/google,lga-usb-phy.yaml | 133 ++++++++++ drivers/phy/Kconfig | 13 + drivers/phy/Makefile | 1 + drivers/phy/phy-google-usb.c | 292 +++++++++++++++++++++ 4 files changed, 439 insertions(+) --- base-commit: 8b690556d8fe074b4f9835075050fba3fb180e93 change-id: 20251119-phyb4-2e03a7c449c4 Best regards, -- Roy Luo -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy