[PATCH 0/8] Add Axiado AX3000 eMMC Host Controller Support

[PATCH 0/8] Add Axiado AX3000 eMMC Host Controller Support

[Tzu-Hao Wei]

This patch series adds support for the eMMC host controller found on
the Axiado AX3000 SoC. The implementation includes support for an
external Arasan eMMC PHY that enables HS200 mode operation at 200 MHz,
significantly improving performance over the default 25 MHz operation.

Hardware Details:

Arasan eMMC host controller on AX3000 SoC
External Arasan eMMC PHY (different from internal PHY supported
by the standard sdhci-of-arasan driver)
Support for HS200 mode (200 MHz) operation
Integration with existing SDHCI framework
Implementation Overview:
The series adds support for the external eMMC PHY required for HS200
mode. The existing sdhci-of-arasan.c driver supports internal PHY
configurations, but the AX3000 uses an external PHY that requires
different configuration. The PHY driver was implemented based on the
reference code in sdhci-pci-arasan.c as recommended by the Arasan team.

This series includes:
1. Device tree bindings for the eMMC PHY
2. PHY driver implementation for the external Arasan eMMC PHY
3. Integration of PHY support into the sdhci-of-arasan host driver
4. Device tree bindings for the eMMC host controller variant
5. Device tree source files for the SoC and EVK board
6. MAINTAINERS file update

Patch series structure:
[1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document
[2/8] phy: axiado: add Arasan eMMC-PHY for Axiado
[3/8] arm64: dts: axiado: Add eMMC-PHY node support
[4/8] MAINTAINERS: Update entry for Axiado eMMC PHY
[5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant
[6/8] mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan
[7/8] arm64: dts: axiado: add common sdhci host node in dtsi
[8/8] arm64: dts: axiado: enable sdhci host

The driver follows the standard Linux PHY framework and integrates
seamlessly with the existing SDHCI subsystem. The implementation
maintains compatibility with the standard Arasan host controller
driver while adding the necessary support for the external PHY.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
SriNavmani A (8):
      dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document
      phy: axiado: add Arasan eMMC-PHY for Axiado
      arm64: dts: axiado: Add eMMC-PHY node support
      MAINTAINERS: Update entry for Axiado eMMC PHY
      dt-bindings: mmc: axiado: Add axiado eMMC variant
      mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan
      arm64: dts: axiado: add common sdhci host node in dtsi
      arm64: dts: axiado: enable sdhci host

 .../devicetree/bindings/mmc/arasan,sdhci.yaml      |  18 ++
 .../bindings/phy/axiado,ax3000-emmc-phy.yaml       |  46 ++++
 MAINTAINERS                                        |  10 +
 arch/arm64/boot/dts/axiado/ax3000-evk.dts          |   8 +
 arch/arm64/boot/dts/axiado/ax3000.dtsi             |  20 ++
 drivers/mmc/host/sdhci-of-arasan.c                 |  20 +-
 drivers/phy/Kconfig                                |   1 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/axiado/Kconfig                         |  15 ++
 drivers/phy/axiado/Makefile                        |   1 +
 drivers/phy/axiado/phy-axiado-emmc.c               | 260 +++++++++++++++++++++
 11 files changed, 393 insertions(+), 7 deletions(-)
---
base-commit: 9448598b22c50c8a5bb77a9103e2d49f134c9578
change-id: 20251222-axiado-ax3000-add-emmc-host-driver-support-2cc84a8f889a

Best regards,
-- 
Tzu-Hao Wei <twei@axiado.com>


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[PATCH 1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add device tree bindings for the Axiado AX3000 eMMC PHY. The bindings
define the required properties for configuring the external Arasan
eMMC PHY, including register base addresses and clock references
needed for HS200 mode operation.

Signed-off-by: SriNavmani A <srinavmani@axiado.com>
Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 .../bindings/phy/axiado,ax3000-emmc-phy.yaml       | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f88941ce60cbd99a73e8c504e0bf36c626bbf674
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/axiado,ax3000-emmc-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado AX3000 Arasan eMMC PHY
+
+maintainers:
+  - SriNavmani A <srinavmani@axiado.com>
+  - Tzu-Hao Wei <twei@axiado.com>
+  - Prasad Bolisetty <pbolisetty@axiado.com>
+
+description: |+
+  Bindings for eMMC PHY on Axiado AX3000 SoC.
+
+  - compatible:         Should be one of the following:
+                        "axiado,ax3000-emmc-phy"
+  - reg:
+      maxItems: 1
+
+properties:
+  compatible:
+    enum:
+      - axiado,ax3000-emmc-phy
+
+  "#phy-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    emmc_phy: emmc-phy@80801C00 {
+        compatible = "axiado,ax3000-emmc-phy";
+        reg = <0x80801C00 0x1000>;
+        #phy-cells = <0>;
+    };

-- 
2.48.1


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Re: [PATCH 1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:00PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Add device tree bindings for the Axiado AX3000 eMMC PHY. The bindings
> define the required properties for configuring the external Arasan
> eMMC PHY, including register base addresses and clock references
> needed for HS200 mode operation.

Do not say what the bindings are supposed to do. We can read the diff.
Explain the hardware.

> 
> Signed-off-by: SriNavmani A <srinavmani@axiado.com>
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> ---
>  .../bindings/phy/axiado,ax3000-emmc-phy.yaml       | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f88941ce60cbd99a73e8c504e0bf36c626bbf674
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/axiado,ax3000-emmc-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Axiado AX3000 Arasan eMMC PHY
> +
> +maintainers:
> +  - SriNavmani A <srinavmani@axiado.com>
> +  - Tzu-Hao Wei <twei@axiado.com>
> +  - Prasad Bolisetty <pbolisetty@axiado.com>
> +
> +description: |+
> +  Bindings for eMMC PHY on Axiado AX3000 SoC.

Irrelevant

> +
> +  - compatible:         Should be one of the following:
> +                        "axiado,ax3000-emmc-phy"
> +  - reg:
> +      maxItems: 1

Entire description is not correct. Do you see any file written like
this/

> +
> +properties:
> +  compatible:
> +    enum:
> +      - axiado,ax3000-emmc-phy
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - "#phy-cells"
> +  - compatible
> +  - reg

Wrong order, use the same as in properties.

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    emmc_phy: emmc-phy@80801C00 {

Drop label and node is just phy@

Also, use lowercase hex everywhere.

Read DTS coding style - Axiado already received this feedback, so you
should follow it in all your submissions.

Best regards,
Krzysztof


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Re: [PATCH 1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document

[Tzu-Hao Wei]

On 12/23/2025 10:23 PM, Krzysztof Kozlowski wrote:
> On Mon, Dec 22, 2025 at 04:45:00PM +0800, Tzu-Hao Wei wrote:
>> From: SriNavmani A <srinavmani@axiado.com>
>>
>> Add device tree bindings for the Axiado AX3000 eMMC PHY. The bindings
>> define the required properties for configuring the external Arasan
>> eMMC PHY, including register base addresses and clock references
>> needed for HS200 mode operation.
> 
> Do not say what the bindings are supposed to do. We can read the diff.
> Explain the hardware.
> 
Simplified the messages in the new patch.

>>
>> Signed-off-by: SriNavmani A <srinavmani@axiado.com>
>> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
>> ---
>>  .../bindings/phy/axiado,ax3000-emmc-phy.yaml       | 46 ++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..f88941ce60cbd99a73e8c504e0bf36c626bbf674
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/axiado,ax3000-emmc-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Axiado AX3000 Arasan eMMC PHY
>> +
>> +maintainers:
>> +  - SriNavmani A <srinavmani@axiado.com>
>> +  - Tzu-Hao Wei <twei@axiado.com>
>> +  - Prasad Bolisetty <pbolisetty@axiado.com>
>> +
>> +description: |+
>> +  Bindings for eMMC PHY on Axiado AX3000 SoC.
> 
> Irrelevant
> 
Removed.

>> +
>> +  - compatible:         Should be one of the following:
>> +                        "axiado,ax3000-emmc-phy"
>> +  - reg:
>> +      maxItems: 1
> 
> Entire description is not correct. Do you see any file written like
> this/
> 
Revised. It can pass DT_SCHEMA_CHECK and CHECK_DTBS now.

>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - axiado,ax3000-emmc-phy
>> +
>> +  "#phy-cells":
>> +    const: 0
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - "#phy-cells"
>> +  - compatible
>> +  - reg
> 
> Wrong order, use the same as in properties.
> 
Fixed.

>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    emmc_phy: emmc-phy@80801C00 {
> 
> Drop label and node is just phy@
> 
> Also, use lowercase hex everywhere.
> 
> Read DTS coding style - Axiado already received this feedback, so you
> should follow it in all your submissions.
> 
> Best regards,
> Krzysztof
> 
Dropped label, used lowercase hex.

Thanks for your feedback.
We will follow the style in the future.

Best regards,
TH


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Re: [PATCH 1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:00PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Add device tree bindings for the Axiado AX3000 eMMC PHY. The bindings
> define the required properties for configuring the external Arasan

Ah, and also:

A nit, subject: drop second/last, redundant "document". The
"dt-bindings" prefix is already stating that these are documents.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

Best regards,
Krzysztof


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Re: [PATCH 1/8] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY document

[Tzu-Hao Wei]

On 12/23/2025 10:23 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
> 
> 
> On Mon, Dec 22, 2025 at 04:45:00PM +0800, Tzu-Hao Wei wrote:
>> From: SriNavmani A <srinavmani@axiado.com>
>>
>> Add device tree bindings for the Axiado AX3000 eMMC PHY. The bindings
>> define the required properties for configuring the external Arasan
> 
> Ah, and also:
> 
> A nit, subject: drop second/last, redundant "document". The
> "dt-bindings" prefix is already stating that these are documents.
> See also:
> https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> 
> Best regards,
> Krzysztof
> 
Revised the subject in the new patch

Best regards,
TH

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[PATCH 2/8] phy: axiado: add Arasan eMMC-PHY for Axiado

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add support for the Arasan eMMC PHY found on the AX3000 SoC. This
external PHY is required to achieve HS200 mode operation (200 MHz)
on the eMMC interface.

The existing sdhci-of-arasan.c driver supports internal PHY
configurations, but the AX3000 uses an external PHY that requires
different configuration. This driver was written based on the
reference implementation in sdhci-pci-arasan.c as suggested by the
Arasan team to provide the necessary PHY configuration for HS200
high-speed mode support.

Signed-off-by: SriNavmani A <srinavmani@axiado.com>
Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 drivers/phy/Kconfig                  |   1 +
 drivers/phy/Makefile                 |   1 +
 drivers/phy/axiado/Kconfig           |  15 ++
 drivers/phy/axiado/Makefile          |   1 +
 drivers/phy/axiado/phy-axiado-emmc.c | 260 +++++++++++++++++++++++++++++++++++
 5 files changed, 278 insertions(+)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0aa0597773433f04d2a9ba77474d2a..b802274ea45a84bd36d7c0b7fb90e368a5c018b4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -103,6 +103,7 @@ config PHY_NXP_PTN3222
 
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
+source "drivers/phy/axiado/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
 source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/freescale/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..f1b9e4a8673bcde3fdc0fdc06a3deddb5785ced1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
 obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o
 obj-y					+= allwinner/	\
 					   amlogic/	\
+					   axiado/	\
 					   broadcom/	\
 					   cadence/	\
 					   freescale/	\
diff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..824114e6068da327308321b9884552ad33db9efc
--- /dev/null
+++ b/drivers/phy/axiado/Kconfig
@@ -0,0 +1,15 @@
+#
+# PHY drivers for Axiado platforms
+#
+
+config PHY_AX3000_EMMC
+	tristate "Axiado eMMC PHY driver"
+	select GENERIC_PHY
+	help
+	  This enables support for the eMMC PHY block found on the
+	  Axiado AX3000 SoCs. The PHY provides the physical layer
+	  interface used by the Arasan SDHCI host controller for emmc
+	  signaling and timing adjustment.
+
+	  If you are building a kernel for AX3000 platform with
+	  eMMC storage, say Y or N.
diff --git a/drivers/phy/axiado/Makefile b/drivers/phy/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1e2b1ba016092eaffdbd7acbd9cdc8577d79b35c
--- /dev/null
+++ b/drivers/phy/axiado/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_AX3000_EMMC)		+= phy-axiado-emmc.o
diff --git a/drivers/phy/axiado/phy-axiado-emmc.c b/drivers/phy/axiado/phy-axiado-emmc.c
new file mode 100644
index 0000000000000000000000000000000000000000..a61a458c9a65915cd576b431bc6a0cf7e8b18add
--- /dev/null
+++ b/drivers/phy/axiado/phy-axiado-emmc.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Axiado eMMC PHY driver
+ *
+ * Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).
+ *
+ * Based on Arasan Driver (sdhci-pci-arasan.c)
+ * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with integrated phy.
+ *
+ * Copyright (C) 2017 Arasan Chip Systems Inc.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+/* Arasan eMMC 5.1 - PHY configuration registers */
+#define CAP_REG_IN_S1_LSB		0x00
+#define CAP_REG_IN_S1_MSB		0x04
+#define PHY_CTRL_1			0x38
+#define PHY_CTRL_2			0x3C
+#define PHY_CTRL_3			0x40
+#define STATUS				0x50
+
+#define DLL_ENBL	BIT(26)
+#define RTRIM_EN	BIT(21)
+#define PDB_ENBL	BIT(23)
+#define RETB_ENBL	BIT(1)
+
+#define REN_STRB	BIT(27)
+#define REN_CMD		BIT(12)
+#define REN_DAT0	BIT(13)
+#define REN_DAT1	BIT(14)
+#define REN_DAT2	BIT(15)
+#define REN_DAT3	BIT(16)
+#define REN_DAT4	BIT(17)
+#define REN_DAT5	BIT(18)
+#define REN_DAT6	BIT(19)
+#define REN_DAT7	BIT(20)
+#define REN_CMD_EN	(REN_CMD | REN_DAT0 | REN_DAT1 | REN_DAT2 | \
+		REN_DAT3 | REN_DAT4 | REN_DAT5 | REN_DAT6 | REN_DAT7)
+
+/* Pull-UP Enable on CMD Line */
+#define PU_CMD		BIT(3)
+#define PU_DAT0		BIT(4)
+#define PU_DAT1		BIT(5)
+#define PU_DAT2		BIT(6)
+#define PU_DAT3		BIT(7)
+#define PU_DAT4		BIT(8)
+#define PU_DAT5		BIT(9)
+#define PU_DAT6		BIT(10)
+#define PU_DAT7		BIT(11)
+#define PU_CMD_EN (PU_CMD | PU_DAT0 | PU_DAT1 | PU_DAT2 | PU_DAT3 | \
+		PU_DAT4 | PU_DAT5 | PU_DAT6 | PU_DAT7)
+
+/* Slection value for the optimum delay from 1-32 output tap lines */
+#define OTAP_DLY	0x02
+/* DLL charge pump current trim default [1000] */
+#define DLL_TRM_ICP	0x08
+/* Select the frequency range of DLL Operation */
+#define FRQ_SEL	0x01
+
+#define OTAP_SEL(x)		(((x) << 7) | OTAPDLY_EN)
+#define DLL_TRM(x)		(((x) << 22) | DLL_ENBL)
+#define DLL_FRQSEL(x)	((x) << 25)
+
+#define OTAPDLY_EN	BIT(11)
+
+#define SEL_DLY_RXCLK	BIT(18)
+#define SEL_DLY_TXCLK	BIT(19)
+
+#define CALDONE_MASK	0x40
+#define DLL_RDY_MASK	0x1
+#define MAX_CLK_BUF0	BIT(20)
+#define MAX_CLK_BUF1	BIT(21)
+#define MAX_CLK_BUF2	BIT(22)
+
+#define CLK_MULTIPLIER	0xC008E
+#define LOOP_TIMEOUT	3000
+#define TIMEOUT_DELAY	100
+
+struct axiado_emmc_phy {
+	void __iomem    *reg_base;
+};
+
+static void arasan_emmc_phy_write(struct axiado_emmc_phy *ax_phy, u32 offset, u32 data)
+{
+	writel(data, ax_phy->reg_base + offset);
+}
+
+static int arasan_emmc_phy_read(struct axiado_emmc_phy *ax_phy, u32 offset)
+{
+	u32 val = readl(ax_phy->reg_base + offset);
+
+	return val;
+}
+
+static int axiado_emmc_phy_init(struct phy *phy)
+{
+	u32 val;
+	ktime_t timeout;
+
+	struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | RETB_ENBL | RTRIM_EN);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | PDB_ENBL);
+
+	/* Wait max 3000 ms */
+	timeout = ktime_add_ms(ktime_get(), LOOP_TIMEOUT);
+
+	while (1) {
+		bool timedout = ktime_after(ktime_get(), timeout);
+
+		if (arasan_emmc_phy_read(ax_phy, STATUS) & CALDONE_MASK)
+			break;
+
+		if (timedout) {
+			dev_err(&phy->dev, "CALDONE_MASK bit is not cleared.");
+			return -ETIMEDOUT;
+		}
+		udelay(TIMEOUT_DELAY);
+	}
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
+
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | REN_CMD_EN | PU_CMD_EN);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_2, val | REN_STRB);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | MAX_CLK_BUF0 |
+			MAX_CLK_BUF1 | MAX_CLK_BUF2);
+
+	val = arasan_emmc_phy_read(ax_phy, CAP_REG_IN_S1_MSB);
+	arasan_emmc_phy_write(ax_phy, CAP_REG_IN_S1_MSB, CLK_MULTIPLIER);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | SEL_DLY_RXCLK |
+			SEL_DLY_TXCLK);
+
+	return 0;
+}
+
+static int axiado_emmc_phy_power_on(struct phy *phy)
+{
+	struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
+
+	u32 val;
+	ktime_t timeout;
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | RETB_ENBL);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | PDB_ENBL);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_2, val | OTAP_SEL(OTAP_DLY));
+
+	arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | DLL_TRM(DLL_TRM_ICP));
+
+	arasan_emmc_phy_write(ax_phy, STATUS, 0x00);
+
+	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
+	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | DLL_FRQSEL(FRQ_SEL));
+
+	/* Wait max 3000 ms */
+	timeout = ktime_add_ms(ktime_get(), LOOP_TIMEOUT);
+
+	while (1) {
+		bool timedout = ktime_after(ktime_get(), timeout);
+
+		if (arasan_emmc_phy_read(ax_phy, STATUS) & DLL_RDY_MASK)
+			break;
+
+		if (timedout) {
+			dev_err(&phy->dev, "DLL_RDY_MASK bit is not cleared.");
+			return -ETIMEDOUT;
+		}
+		udelay(TIMEOUT_DELAY);
+	}
+	return 0;
+}
+
+static const struct phy_ops axiado_emmc_phy_ops = {
+	.init		= axiado_emmc_phy_init,
+	.power_on	= axiado_emmc_phy_power_on,
+	.owner		= THIS_MODULE,
+};
+
+static const struct of_device_id axiado_emmc_phy_of_match[] = {
+	{ .compatible = "axiado,ax3000-emmc-phy"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, axiado_emmc_phy_of_match);
+
+static int axiado_emmc_phy_probe(struct platform_device *pdev)
+{
+	struct axiado_emmc_phy *ax_phy;
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	const struct of_device_id *id;
+	struct phy *generic_phy;
+	struct resource *res;
+
+	if (!dev->of_node)
+		return -ENODEV;
+
+	ax_phy = devm_kzalloc(dev, sizeof(*ax_phy), GFP_KERNEL);
+	if (!ax_phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	ax_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
+
+	if (IS_ERR(ax_phy->reg_base))
+		return PTR_ERR(ax_phy->reg_base);
+
+	id = of_match_node(axiado_emmc_phy_of_match, pdev->dev.of_node);
+	if (!id) {
+		dev_err(dev, "failed to get match_node\n");
+		return -EINVAL;
+	}
+
+	generic_phy = devm_phy_create(dev, dev->of_node, &axiado_emmc_phy_ops);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(generic_phy);
+	}
+
+	phy_set_drvdata(generic_phy, ax_phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver axiado_emmc_phy_driver = {
+	.probe		 = axiado_emmc_phy_probe,
+	.driver		 = {
+		.name	 = "axiado-emmc-phy",
+		.of_match_table = axiado_emmc_phy_of_match,
+	},
+};
+module_platform_driver(axiado_emmc_phy_driver);
+
+MODULE_DESCRIPTION("AX3000 eMMC PHY Driver");
+MODULE_AUTHOR("Axiado Corporation");
+MODULE_LICENSE("GPL");

-- 
2.48.1


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Re: [PATCH 2/8] phy: axiado: add Arasan eMMC-PHY for Axiado

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:01PM +0800, Tzu-Hao Wei wrote:
> @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
>  obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o


Where is maintainers file update in this patch? Why shall we take
unmaintained code?

>  obj-y					+= allwinner/	\
>  					   amlogic/	\
> +					   axiado/	\
>  					   broadcom/	\
>  					   cadence/	\
>  					   freescale/	\
> diff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..824114e6068da327308321b9884552ad33db9efc
> --- /dev/null
> +++ b/drivers/phy/axiado/Kconfig
> @@ -0,0 +1,15 @@
> +#
> +# PHY drivers for Axiado platforms
> +#
> +

Missing menuconfig or other if-block for groupping this with your ARCH
and COMPILE_TEST dependency.

Look how other NEW and MAINTAINED platforms did it.

> +config PHY_AX3000_EMMC
> +	tristate "Axiado eMMC PHY driver"
> +	select GENERIC_PHY
> +	help
> +	  This enables support for the eMMC PHY block found on the
> +	  Axiado AX3000 SoCs. The PHY provides the physical layer
> +	  interface used by the Arasan SDHCI host controller for emmc
> +	  signaling and timing adjustment.
> +
> +	  If you are building a kernel for AX3000 platform with
> +	  eMMC storage, say Y or N.

...


> +static void arasan_emmc_phy_write(struct axiado_emmc_phy *ax_phy, u32 offset, u32 data)
> +{
> +	writel(data, ax_phy->reg_base + offset);
> +}
> +
> +static int arasan_emmc_phy_read(struct axiado_emmc_phy *ax_phy, u32 offset)

Useless wrappers. Just use readl/writel directly. You are not making
code more readable.

> +{
> +	u32 val = readl(ax_phy->reg_base + offset);
> +
> +	return val;
> +}
> +
> +static int axiado_emmc_phy_init(struct phy *phy)
> +{
> +	u32 val;
> +	ktime_t timeout;
> +
> +	struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | RETB_ENBL | RTRIM_EN);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | PDB_ENBL);
> +
> +	/* Wait max 3000 ms */
> +	timeout = ktime_add_ms(ktime_get(), LOOP_TIMEOUT);
> +
> +	while (1) {
> +		bool timedout = ktime_after(ktime_get(), timeout);
> +
> +		if (arasan_emmc_phy_read(ax_phy, STATUS) & CALDONE_MASK)
> +			break;
> +
> +		if (timedout) {
> +			dev_err(&phy->dev, "CALDONE_MASK bit is not cleared.");
> +			return -ETIMEDOUT;
> +		}
> +		udelay(TIMEOUT_DELAY);
> +	}
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
> +
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | REN_CMD_EN | PU_CMD_EN);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_2, val | REN_STRB);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | MAX_CLK_BUF0 |
> +			MAX_CLK_BUF1 | MAX_CLK_BUF2);
> +
> +	val = arasan_emmc_phy_read(ax_phy, CAP_REG_IN_S1_MSB);
> +	arasan_emmc_phy_write(ax_phy, CAP_REG_IN_S1_MSB, CLK_MULTIPLIER);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | SEL_DLY_RXCLK |
> +			SEL_DLY_TXCLK);
> +
> +	return 0;
> +}
> +
> +static int axiado_emmc_phy_power_on(struct phy *phy)
> +{
> +	struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> +
> +	u32 val;
> +	ktime_t timeout;
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | RETB_ENBL);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | PDB_ENBL);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_2, val | OTAP_SEL(OTAP_DLY));
> +
> +	arasan_emmc_phy_read(ax_phy, PHY_CTRL_2);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_1);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_1, val | DLL_TRM(DLL_TRM_ICP));
> +
> +	arasan_emmc_phy_write(ax_phy, STATUS, 0x00);
> +
> +	val = arasan_emmc_phy_read(ax_phy, PHY_CTRL_3);
> +	arasan_emmc_phy_write(ax_phy, PHY_CTRL_3, val | DLL_FRQSEL(FRQ_SEL));
> +
> +	/* Wait max 3000 ms */
> +	timeout = ktime_add_ms(ktime_get(), LOOP_TIMEOUT);
> +
> +	while (1) {

You proper read_poll loop.

> +		bool timedout = ktime_after(ktime_get(), timeout);
> +
> +		if (arasan_emmc_phy_read(ax_phy, STATUS) & DLL_RDY_MASK)
> +			break;
> +
> +		if (timedout) {
> +			dev_err(&phy->dev, "DLL_RDY_MASK bit is not cleared.");
> +			return -ETIMEDOUT;
> +		}
> +		udelay(TIMEOUT_DELAY);

...

> +static int axiado_emmc_phy_probe(struct platform_device *pdev)
> +{
> +	struct axiado_emmc_phy *ax_phy;
> +	struct phy_provider *phy_provider;
> +	struct device *dev = &pdev->dev;
> +	const struct of_device_id *id;
> +	struct phy *generic_phy;
> +	struct resource *res;
> +
> +	if (!dev->of_node)
> +		return -ENODEV;
> +
> +	ax_phy = devm_kzalloc(dev, sizeof(*ax_phy), GFP_KERNEL);
> +	if (!ax_phy)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +

Use proper wrapper to combine get resource and ioremap.

> +	ax_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
> +

Drop blank line, there's never such.

> +	if (IS_ERR(ax_phy->reg_base))
> +		return PTR_ERR(ax_phy->reg_base);
> +
> +	id = of_match_node(axiado_emmc_phy_of_match, pdev->dev.of_node);
> +	if (!id) {
> +		dev_err(dev, "failed to get match_node\n");

What is the point of this? You do not use this match at all, no other
devices. How can your device bind and still fail the match?

Drop

> +		return -EINVAL;
> +	}
> +
> +	generic_phy = devm_phy_create(dev, dev->of_node, &axiado_emmc_phy_ops);
> +	if (IS_ERR(generic_phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(generic_phy);

Syntax is - return dev_err_probe.

Didn't Axiado receive this feedback before? Are you sure that you have
procedures set inside to avoid repeating same mistakes?

Best regards,
Krzysztof


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Re: [PATCH 2/8] phy: axiado: add Arasan eMMC-PHY for Axiado

[Tzu-Hao Wei]

On 12/23/2025 10:32 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
> 
> 
> On Mon, Dec 22, 2025 at 04:45:01PM +0800, Tzu-Hao Wei wrote:
>> @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE)               += phy-airoha-pcie.o
>>  obj-$(CONFIG_PHY_NXP_PTN3222)                += phy-nxp-ptn3222.o
> 
> 
> Where is maintainers file update in this patch? Why shall we take
> unmaintained code?
> 
It's in this series 4/8.

>>  obj-y                                        += allwinner/   \
>>                                          amlogic/     \
>> +                                        axiado/      \
>>                                          broadcom/    \
>>                                          cadence/     \
>>                                          freescale/   \
>> diff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..824114e6068da327308321b9884552ad33db9efc
>> --- /dev/null
>> +++ b/drivers/phy/axiado/Kconfig
>> @@ -0,0 +1,15 @@
>> +#
>> +# PHY drivers for Axiado platforms
>> +#
>> +
> 
> Missing menuconfig or other if-block for groupping this with your ARCH
> and COMPILE_TEST dependency.
> 
Updated in the next version with
depends on OF && (ARCH_AXIADO || COMPILE_TEST)

> Look how other NEW and MAINTAINED platforms did it.
> 
>> +config PHY_AX3000_EMMC
>> +     tristate "Axiado eMMC PHY driver"
>> +     select GENERIC_PHY
>> +     help
>> +       This enables support for the eMMC PHY block found on the
>> +       Axiado AX3000 SoCs. The PHY provides the physical layer
>> +       interface used by the Arasan SDHCI host controller for emmc
>> +       signaling and timing adjustment.
>> +
>> +       If you are building a kernel for AX3000 platform with
>> +       eMMC storage, say Y or N.
> 
> ...
> 
> 
Clean up the description in the new patch.

>> +static void arasan_emmc_phy_write(struct axiado_emmc_phy *ax_phy, u32 offset, u32 data)
>> +{
>> +     writel(data, ax_phy->reg_base + offset);
>> +}
>> +
>> +static int arasan_emmc_phy_read(struct axiado_emmc_phy *ax_phy, u32 offset)
> 
> Useless wrappers. Just use readl/writel directly. You are not making
> code more readable.
> 
Removed wrappers and use readl/writel directly.

>> +
>> +     while (1) {
> 
> You proper read_poll loop.
Removed while() and use readl_poll_timeout()

>> +             bool timedout = ktime_after(ktime_get(), timeout);
>> +
>> +             if (arasan_emmc_phy_read(ax_phy, STATUS) & DLL_RDY_MASK)
>> +                     break;
>> +
>> +             if (timedout) {
>> +                     dev_err(&phy->dev, "DLL_RDY_MASK bit is not cleared.");
>> +                     return -ETIMEDOUT;
>> +             }
>> +             udelay(TIMEOUT_DELAY);
> 
> ...
> 
Removed.

>> +static int axiado_emmc_phy_probe(struct platform_device *pdev)
>> +{
>> +     struct axiado_emmc_phy *ax_phy;
>> +     struct phy_provider *phy_provider;
>> +     struct device *dev = &pdev->dev;
>> +     const struct of_device_id *id;
>> +     struct phy *generic_phy;
>> +     struct resource *res;
>> +
>> +     if (!dev->of_node)
>> +             return -ENODEV;
>> +
>> +     ax_phy = devm_kzalloc(dev, sizeof(*ax_phy), GFP_KERNEL);
>> +     if (!ax_phy)
>> +             return -ENOMEM;
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
> 
> Use proper wrapper to combine get resource and ioremap.
> 
Fixed.
Calling devm_platform_ioremap_resource(pdev, 0) now.

>> +     ax_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
>> +
> 
> Drop blank line, there's never such.
> 
Removed
>> +     if (IS_ERR(ax_phy->reg_base))
>> +             return PTR_ERR(ax_phy->reg_base);
>> +
>> +     id = of_match_node(axiado_emmc_phy_of_match, pdev->dev.of_node);
>> +     if (!id) {
>> +             dev_err(dev, "failed to get match_node\n");
> 
> What is the point of this? You do not use this match at all, no other
> devices. How can your device bind and still fail the match?
> 
> Drop
> 
Removed.

>> +             return -EINVAL;
>> +     }
>> +
>> +     generic_phy = devm_phy_create(dev, dev->of_node, &axiado_emmc_phy_ops);
>> +     if (IS_ERR(generic_phy)) {
>> +             dev_err(dev, "failed to create PHY\n");
>> +             return PTR_ERR(generic_phy);
> 
> Syntax is - return dev_err_probe.
> 
Fixed.

> Didn't Axiado receive this feedback before? Are you sure that you have
> procedures set inside to avoid repeating same mistakes?
> 
> Best regards,
> Krzysztof
> 
Thanks Krzysztof.

I have checked the comments one-by-one and make sure every comments
are adopted.

Best regards,
TH

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[PATCH 3/8] arm64: dts: axiado: Add eMMC-PHY node support

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add the eMMC PHY device tree node to the AX3000 SoC device tree
include file. This node defines the external Arasan eMMC PHY
configuration required for HS200 mode operation.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 arch/arm64/boot/dts/axiado/ax3000.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
index 792f52e0c7dd42cbc54b0eb47e25b0fbf1a706b8..0b64cf1245211ab0e9380dc27dae37dd9f3082e8 100644
--- a/arch/arm64/boot/dts/axiado/ax3000.dtsi
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -507,6 +507,13 @@ uart3: serial@80520800 {
 			clocks = <&refclk &refclk>;
 			status = "disabled";
 		};
+
+		emmc_phy: emmc-phy@80801C00 {
+			compatible = "axiado,ax3000-emmc-phy";
+			reg = <0x00 0x80801C00 0x00 0x1000>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
 	};
 
 	timer {

-- 
2.48.1


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[PATCH 4/8] MAINTAINERS: Update entry for Axiado eMMC PHY

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Update the MAINTAINERS file to include the Axiado eMMC PHY driver
files. This includes the PHY driver source files, device tree
bindings, and related configuration files for the AX3000 eMMC PHY
support.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dc731d37c8feeff25613c59fe9c929927dadaa7e..d14f2d1c94bc65879c922401366f98a812dd3ba9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4250,6 +4250,16 @@ W:	https://ez.analog.com/linux-software-drivers
 F:	Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml
 F:	drivers/hwmon/axi-fan-control.c
 
+AXIADO EMMC PHY DRIVER
+M:	SriNavmani A <srinavmani@axiado.com>
+M:	Tzu-Hao Wei <twei@axiado.com>
+M:	Prasad Bolisetty <pbolisetty@axiado.com>
+L:	linux-phy@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml
+F:	drivers/phy/axiado/Kconfig
+F:	drivers/phy/axiado/phy-axiado-emmc.c
+
 AXI SPI ENGINE
 M:	Michael Hennerich <michael.hennerich@analog.com>
 M:	Nuno Sá <nuno.sa@analog.com>

-- 
2.48.1


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[PATCH 5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add device tree binding variant for the Axiado AX3000 Arasan eMMC
controller. This variant identifies the specific eMMC controller
implementation used on the AX3000 SoC and enables the appropriate
driver configuration.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.yaml          | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 8e79de97b242a698a2c555b0b94e2975b1761710..47d0e35efea00bf7b1927bd0cfa39c86f0137d44 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -106,6 +106,12 @@ properties:
         description:
           For this device it is strongly suggested to include
           arasan,soc-ctl-syscon.
+      - items:
+          - const: axiado,ax3000-sdhci-5.1-emmc
+          - const: arasan,sdhci-5.1
+        description:
+          For this device it is strongly suggested to include
+          clock-output-names and '#clock-cells'.
 
   reg:
     maxItems: 1
@@ -334,3 +340,15 @@ examples:
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
     };
+
+  - |
+    mmc@86000000 {
+          compatible = "axiado,ax3000-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+          reg = <0x86000000 0x1000>;
+          clock-names = "clk_xin", "clk_ahb";
+          clocks = <&clk_xin &clk_ahb>;
+          interrupt-parent = <&gic500>;
+          interrupts = <0 123 4>;
+          phys = <&emmc_phy>;
+          phy-names = "phy_arasan";
+    };

-- 
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Re: [PATCH 5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:04PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Add device tree binding variant for the Axiado AX3000 Arasan eMMC
> controller. This variant identifies the specific eMMC controller
> implementation used on the AX3000 SoC and enables the appropriate
> driver configuration.
> 
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> ---
>  .../devicetree/bindings/mmc/arasan,sdhci.yaml          | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> index 8e79de97b242a698a2c555b0b94e2975b1761710..47d0e35efea00bf7b1927bd0cfa39c86f0137d44 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -106,6 +106,12 @@ properties:
>          description:
>            For this device it is strongly suggested to include
>            arasan,soc-ctl-syscon.
> +      - items:
> +          - const: axiado,ax3000-sdhci-5.1-emmc
> +          - const: arasan,sdhci-5.1
> +        description:
> +          For this device it is strongly suggested to include
> +          clock-output-names and '#clock-cells'.
>  
>    reg:
>      maxItems: 1
> @@ -334,3 +340,15 @@ examples:
>                     <&scmi_clk KEEM_BAY_PSS_SD0>;
>            arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
>      };
> +
> +  - |
> +    mmc@86000000 {

No need for a new example. Please writing bindings and writing schema
docs first.

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Krzysztof


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Re: [PATCH 5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant

[Tzu-Hao Wei]

On 12/23/2025 10:43 PM, Krzysztof Kozlowski wrote:
> 
> No need for a new example. Please writing bindings and writing schema
> docs first.
> 
> Best regards,
> Krzysztof
> 
Thanks. Removed.


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Re: [PATCH 5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:04PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Add device tree binding variant for the Axiado AX3000 Arasan eMMC
> controller. This variant identifies the specific eMMC controller
> implementation used on the AX3000 SoC and enables the appropriate
> driver configuration.
> 
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>

Incorrect DCO chain.


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Re: [PATCH 5/8] dt-bindings: mmc: axiado: Add axiado eMMC variant

[Tzu-Hao Wei]

On 12/27/2025 8:50 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
> 
> 
> On Mon, Dec 22, 2025 at 04:45:04PM +0800, Tzu-Hao Wei wrote:
>> From: SriNavmani A <srinavmani@axiado.com>
>>
>> Add device tree binding variant for the Axiado AX3000 Arasan eMMC
>> controller. This variant identifies the specific eMMC controller
>> implementation used on the AX3000 SoC and enables the appropriate
>> driver configuration.
>>
>> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> 
> Incorrect DCO chain.
> 
> 
> Best regards,
> Krzysztof
> 
Fixed DOC chain in the new patchset.

Best regards,
TH

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[PATCH 6/8] mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add support for the external eMMC PHY used on the AX3000 SoC in the
sdhci-of-arasan driver. The default Arasan host driver operates at
25 MHz, but with the external PHY support, the controller can achieve
HS200 mode operation at 200 MHz.

This change integrates the AX3000 eMMC PHY driver with the existing
sdhci-of-arasan host controller driver to enable high-speed eMMC
operations.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index ab7f0ffe7b4f007a58eb0a26868b08b0b02b40f3..2d4f64e9014ae168957113478edc11209cd76b64 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -1547,6 +1547,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
 		.compatible = "arasan,sdhci-5.1",
 		.data = &sdhci_arasan_generic_data,
 	},
+	{
+		.compatible = "axiado,ax3000-sdhci-5.1-emmc",
+		.data = &sdhci_arasan_generic_data,
+	},
 	{
 		.compatible = "arasan,sdhci-4.9a",
 		.data = &sdhci_arasan_generic_data,
@@ -2019,15 +2023,17 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 			goto unreg_clk;
 		}
 
-		host->mmc_host_ops.hs400_enhanced_strobe =
+		if (!of_device_is_compatible(np, "axiado,ax3000-sdhci-5.1-emmc")) {
+			host->mmc_host_ops.hs400_enhanced_strobe =
 					sdhci_arasan_hs400_enhanced_strobe;
-		host->mmc_host_ops.start_signal_voltage_switch =
-					sdhci_arasan_voltage_switch;
-		sdhci_arasan->has_cqe = true;
-		host->mmc->caps2 |= MMC_CAP2_CQE;
+			host->mmc_host_ops.start_signal_voltage_switch =
+				sdhci_arasan_voltage_switch;
+			sdhci_arasan->has_cqe = true;
+			host->mmc->caps2 |= MMC_CAP2_CQE;
 
-		if (!of_property_read_bool(np, "disable-cqe-dcmd"))
-			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
+			if (!of_property_read_bool(np, "disable-cqe-dcmd"))
+				host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
+		}
 	}
 
 	if (of_device_is_compatible(np, "xlnx,versal-net-emmc"))

-- 
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Re: [PATCH 6/8] mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:05PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Add support for the external eMMC PHY used on the AX3000 SoC in the
> sdhci-of-arasan driver. The default Arasan host driver operates at
> 25 MHz, but with the external PHY support, the controller can achieve
> HS200 mode operation at 200 MHz.
> 
> This change integrates the AX3000 eMMC PHY driver with the existing
> sdhci-of-arasan host controller driver to enable high-speed eMMC
> operations.
> 
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 20 +++++++++++++-------

Why do you mix mmc, phy and soc into one patchset?

>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index ab7f0ffe7b4f007a58eb0a26868b08b0b02b40f3..2d4f64e9014ae168957113478edc11209cd76b64 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -1547,6 +1547,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
>  		.compatible = "arasan,sdhci-5.1",
>  		.data = &sdhci_arasan_generic_data,
>  	},
> +	{
> +		.compatible = "axiado,ax3000-sdhci-5.1-emmc",
> +		.data = &sdhci_arasan_generic_data,
> +	},
>  	{
>  		.compatible = "arasan,sdhci-4.9a",
>  		.data = &sdhci_arasan_generic_data,
> @@ -2019,15 +2023,17 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>  			goto unreg_clk;
>  		}
>  
> -		host->mmc_host_ops.hs400_enhanced_strobe =
> +		if (!of_device_is_compatible(np, "axiado,ax3000-sdhci-5.1-emmc")) {

No, don't sprinkle compatibles all around. You should use driver match
data for this.

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Krzysztof


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Re: [PATCH 6/8] mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan

[Tzu-Hao Wei]

On 12/23/2025 10:34 PM, Krzysztof Kozlowski wrote:
>> @@ -2019,15 +2023,17 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>>                       goto unreg_clk;
>>               }
>>
>> -             host->mmc_host_ops.hs400_enhanced_strobe =
>> +             if (!of_device_is_compatible(np, "axiado,ax3000-sdhci-5.1-emmc")) {
> 
> No, don't sprinkle compatibles all around. You should use driver match
> data for this.
> 
> Best regards,
> Krzysztof
> 
Thanks for suggestion. The new patch uses driver match data instead of sprinkling compatibles.

Best regards,
TH

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Re: [PATCH 6/8] mmc: host: axiado: add AX3000 eMMC PHY support to sdhci-of-arasan

[Krzysztof Kozlowski]

On 05/02/2026 04:36, Tzu-Hao Wei wrote:
> On 12/23/2025 10:34 PM, Krzysztof Kozlowski wrote:
>>> @@ -2019,15 +2023,17 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>>>                       goto unreg_clk;
>>>               }
>>>
>>> -             host->mmc_host_ops.hs400_enhanced_strobe =
>>> +             if (!of_device_is_compatible(np, "axiado,ax3000-sdhci-5.1-emmc")) {
>>
>> No, don't sprinkle compatibles all around. You should use driver match
>> data for this.
>>
>> Best regards,
>> Krzysztof
>>
> Thanks for suggestion. The new patch uses driver match data instead of sprinkling compatibles.

You replied to a review from more than a month ago, even though I gave
you review after one day. I don't have anything of this in my inbox, so
in case you asked of something - I still expect all feedback to be
implemented.

Best regards,
Krzysztof

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[PATCH 7/8] arm64: dts: axiado: add common sdhci host node in dtsi

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Add the SDHCI host controller device tree node to the AX3000 SoC
device tree include file. This node defines the Arasan eMMC host
controller configuration, including register mappings, interrupts,
and clock references for the AX3000 SoC.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 arch/arm64/boot/dts/axiado/ax3000.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
index 0b64cf1245211ab0e9380dc27dae37dd9f3082e8..b963537001155d825f878156b2f930b202da1723 100644
--- a/arch/arm64/boot/dts/axiado/ax3000.dtsi
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -514,6 +514,19 @@ emmc_phy: emmc-phy@80801C00 {
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+
+		sdhci0: mmc@86000000 {
+			compatible = "axiado,ax3000-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+			reg = <0x0 0x86000000 0x00 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&clk_xin &clk_xin>;
+			interrupt-parent = <&gic500>;
+			interrupts = <0 123 4>;
+			bus-width = <8>;
+			phys = <&emmc_phy>;
+			phy-names = "phy_arasan";
+			status = "disabled";
+		};
 	};
 
 	timer {

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[PATCH 8/8] arm64: dts: axiado: enable sdhci host

[Tzu-Hao Wei]

From: SriNavmani A <srinavmani@axiado.com>

Enable the SDHCI host controller for eMMC support on the AX3000 EVK
evaluation board by referencing the SDHCI node defined in the SoC
device tree include file. This enables eMMC functionality on the
evaluation board.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
---
 arch/arm64/boot/dts/axiado/ax3000-evk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
index b86e969625573bf92bdd5e4435ea571dd7500de2..a5cc75dfbe554749201b0910ec268c899bc5246c 100644
--- a/arch/arm64/boot/dts/axiado/ax3000-evk.dts
+++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
@@ -80,3 +80,11 @@ &uart2 {
 &uart3 {
 	status = "okay";
 };
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdhci0 {
+	status = "okay";
+};

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Re: [PATCH 8/8] arm64: dts: axiado: enable sdhci host

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:45:07PM +0800, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
> 
> Enable the SDHCI host controller for eMMC support on the AX3000 EVK
> evaluation board by referencing the SDHCI node defined in the SoC
> device tree include file. This enables eMMC functionality on the
> evaluation board.
> 
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>

Why DTS is both BEFORE and AFTER drivers? This is a total mess.


> ---
>  arch/arm64/boot/dts/axiado/ax3000-evk.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> index b86e969625573bf92bdd5e4435ea571dd7500de2..a5cc75dfbe554749201b0910ec268c899bc5246c 100644
> --- a/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> +++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> @@ -80,3 +80,11 @@ &uart2 {
>  &uart3 {
>  	status = "okay";
>  };
> +
> +&emmc_phy {

Axiado already received comment to read DTS coding style. Did you read
it?

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Re: [PATCH 0/8] Add Axiado AX3000 eMMC Host Controller Support

[Krzysztof Kozlowski]

On Mon, Dec 22, 2025 at 04:44:59PM +0800, Tzu-Hao Wei wrote:
> This patch series adds support for the eMMC host controller found on
> the Axiado AX3000 SoC. The implementation includes support for an
> external Arasan eMMC PHY that enables HS200 mode operation at 200 MHz,
> significantly improving performance over the default 25 MHz operation.
> 
> Hardware Details:
> 
> Arasan eMMC host controller on AX3000 SoC
> External Arasan eMMC PHY (different from internal PHY supported
> by the standard sdhci-of-arasan driver)
> Support for HS200 mode (200 MHz) operation
> Integration with existing SDHCI framework
> Implementation Overview:
> The series adds support for the external eMMC PHY required for HS200
> mode. The existing sdhci-of-arasan.c driver supports internal PHY
> configurations, but the AX3000 uses an external PHY that requires
> different configuration. The PHY driver was implemented based on the
> reference code in sdhci-pci-arasan.c as recommended by the Arasan team.
> 
> This series includes:
> 1. Device tree bindings for the eMMC PHY
> 2. PHY driver implementation for the external Arasan eMMC PHY
> 3. Integration of PHY support into the sdhci-of-arasan host driver
> 4. Device tree bindings for the eMMC host controller variant
> 5. Device tree source files for the SoC and EVK board
> 6. MAINTAINERS file update

You completely disorganized the patch.. dts is mixed all over driver
code, you combined two or three completely independent subsystems into
one.

Read submitting patches in DT dir to understand how DTS must be sent.


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Re: [PATCH 0/8] Add Axiado AX3000 eMMC Host Controller Support

[Tzu-Hao Wei]

On 12/23/2025 10:33 PM, Krzysztof Kozlowski wrote:
> 
> You completely disorganized the patch.. dts is mixed all over driver
> code, you combined two or three completely independent subsystems into
> one.
> 
> Read submitting patches in DT dir to understand how DTS must be sent.
> 
> 
> Best regards,
> Krzysztof
> 
Hi Krzysztof,

Appreciate your review comments. We reorganized the patch series per your review comments, separating the DTS changes and applying the driver code changes to the respective subsystems as following
https://lore.kernel.org/all/20260109-axiado-ax3000-add-emmc-phy-driver-support-v1-0-dd43459dbfea@axiado.com/
https://lore.kernel.org/all/20260109-axiado-ax3000-add-emmc-host-driver-support-v2-0-934f1a61f7c0@axiado.com/

We will also sync up internally and tighten our review process to ensure this kind of mistake does not happen again in future submissions.

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TH

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Re: [PATCH 0/8] Add Axiado AX3000 eMMC Host Controller Support

[Krzysztof Kozlowski]

On 09/01/2026 10:48, Tzu-Hao Wei wrote:
> On 12/23/2025 10:33 PM, Krzysztof Kozlowski wrote:
>>
>> You completely disorganized the patch.. dts is mixed all over driver
>> code, you combined two or three completely independent subsystems into
>> one.
>>
>> Read submitting patches in DT dir to understand how DTS must be sent.
>>
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
> 
> Appreciate your review comments. We reorganized the patch series per your review comments, separating the DTS changes and applying the driver code changes to the respective subsystems as following

Please wrap your emails correctly.

> https://lore.kernel.org/all/20260109-axiado-ax3000-add-emmc-phy-driver-support-v1-0-dd43459dbfea@axiado.com/


You sent this as v1, which I noticed only now. If I knew you ignored my
feedback, I would not care to review again... Lesson for me.

> https://lore.kernel.org/all/20260109-axiado-ax3000-add-emmc-host-driver-support-v2-0-934f1a61f7c0@axiado.com/
> 
> We will also sync up internally and tighten our review process to ensure this kind of mistake does not happen again in future submissions.

Best regards,
Krzysztof

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