[PATCH] phy: cadence: Sierra: Do not modify register when getting parent clock

[PATCH] phy: cadence: Sierra: Do not modify register when getting parent clock

[Gregory CLEMENT]

The get_parent() callback for the PLL_CMNLC1 clock was incorrectly
writing to the register while determining the parent clock index. This
unintended register access forces the PHY back into training mode. If
the PHY is already configured, this unexpected change prevents it from
exiting training mode.

Remove the register write operation to ensure the PHY remains stable
during the get_parent() callback.

Fixes: da08aab940092 ("phy: cadence: Sierra: Fix to get correct parent for mux clocks")
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 drivers/phy/cadence/phy-cadence-sierra.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 92ab1a31646ae..d4e8979c3abba 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -706,15 +706,10 @@ static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
 
 	regmap_field_read(field, &val);
 
-	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
+	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
 		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
-		if (index == 1) {
-			regmap_field_write(plllc1en_field, 1);
-			regmap_field_write(termen_field, 1);
-		}
-	} else {
+	else
 		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
-	}
 
 	return index;
 }

---
base-commit: 11439c4635edd669ae435eec308f4ab8a0804808
change-id: 20260305-fix_sierra_get_parent-9c8435cc65e7

Best regards,
-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


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Re: [PATCH] phy: cadence: Sierra: Do not modify register when getting parent clock

[kernel test robot]

Hi Gregory,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]

url:    https://github.com/intel-lab-lkp/linux/commits/Gregory-CLEMENT/phy-cadence-Sierra-Do-not-modify-register-when-getting-parent-clock/20260306-000915
base:   11439c4635edd669ae435eec308f4ab8a0804808
patch link:    https://lore.kernel.org/r/20260305-fix_sierra_get_parent-v1-1-a7c18e9e6c58%40bootlin.com
patch subject: [PATCH] phy: cadence: Sierra: Do not modify register when getting parent clock
config: xtensa-randconfig-001-20260306 (https://download.01.org/0day-ci/archive/20260306/202603061235.hrl27Jvj-lkp@intel.com/config)
compiler: xtensa-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260306/202603061235.hrl27Jvj-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603061235.hrl27Jvj-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/phy/cadence/phy-cadence-sierra.c: In function 'cdns_sierra_pll_mux_get_parent':
>> drivers/phy/cadence/phy-cadence-sierra.c:702:23: warning: unused variable 'termen_field' [-Wunused-variable]
     struct regmap_field *termen_field = mux->termen_field;
                          ^~~~~~~~~~~~
>> drivers/phy/cadence/phy-cadence-sierra.c:701:23: warning: unused variable 'plllc1en_field' [-Wunused-variable]
     struct regmap_field *plllc1en_field = mux->plllc1en_field;
                          ^~~~~~~~~~~~~~


vim +/termen_field +702 drivers/phy/cadence/phy-cadence-sierra.c

d88ca22d6f0c924 Aswath Govindraju      2022-01-28  697  
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  698  static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  699  {
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  700  	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
da08aab940092a0 Swapnil Jakhade        2021-12-23 @701  	struct regmap_field *plllc1en_field = mux->plllc1en_field;
da08aab940092a0 Swapnil Jakhade        2021-12-23 @702  	struct regmap_field *termen_field = mux->termen_field;
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  703  	struct regmap_field *field = mux->pfdclk_sel_preg;
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  704  	unsigned int val;
da08aab940092a0 Swapnil Jakhade        2021-12-23  705  	int index;
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  706  
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  707  	regmap_field_read(field, &val);
da08aab940092a0 Swapnil Jakhade        2021-12-23  708  
4f20466dcc453ec Gregory CLEMENT        2026-03-05  709  	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
da08aab940092a0 Swapnil Jakhade        2021-12-23  710  		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
4f20466dcc453ec Gregory CLEMENT        2026-03-05  711  	else
da08aab940092a0 Swapnil Jakhade        2021-12-23  712  		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
da08aab940092a0 Swapnil Jakhade        2021-12-23  713  
da08aab940092a0 Swapnil Jakhade        2021-12-23  714  	return index;
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  715  }
28081b72859f0fa Kishon Vijay Abraham I 2021-03-19  716  

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