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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f88885b87dsm5033122eec.21.2026.05.08.16.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 16:31:22 -0700 (PDT) From: Matthew Leung Subject: [PATCH 00/10] phy: qcom: qmp-pcie: Add PCIe PHY support for Hawi Date: Fri, 08 May 2026 23:31:15 +0000 Message-Id: <20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAERy/mkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDUwMz3YzE8kzdgoxK3YLkzFRdIwtjS2PjJBNDQ+NUJaCegqLUtMwKsHn RsRB+cWlSVmpyCcgQpdpaAOIItllxAAAA X-Change-ID: 20260506-hawi-phy-pcie-283933b4113e To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778283082; l=2557; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=FpOZVILuZdKgJAFxsw9h/rPIUNFgYb8dRtvt8QqP9Z0=; b=zISOr8IB5ta3VgjDqkWMsbaZncXLlgITdeAIOxr1F6HLT9iX94noIF3XhYRlttW32yw5rlE5m DAb3mVjQeKfCTa88BX+irQNytlAtLaNU8tzuew6K2KAtfaQ+l/vmAye X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDIzMiBTYWx0ZWRfX3Bla8dpie+Mt Sj5a9uw+sX8jwJ5jYCb49b/np8SvwtmTbPhD9dUXQ5RmEcH5GtJGXd3iH/u0h+ydmLJElfSoice e/YrGn0qN13Iq5DTSWI0jBoeReDU5Ug+CyKl2rayhZlYpUqJFYORFCUFXxPuRbSw0PRfzG3fgSx 4S1gOnJ0yZGty5IQKBJ4Yr2YgFYuRDs5ESlFf704U4V7afvTXPwZ0OyD9OSZ5d28YEFkBDKsDdn N9J8pq/26wj8/htRyWG1h0rlFmi4+rsX4C56lNwi/pywnt1y/39UM5DK4qe06ORziAvdzEu7q4X fy3AWY/AKwjEMKiYcnTkC0U6agyGgQ57JtFo/v2VojcjsMKYYBoorbMeR1TuFs3tK/gPCI5leng qPbeXj4inAZiPxOjP+BEG8Jt7WeB97I1UOemjctFskNeh5Rr6KBeKHs2rUD9lpFt7XxJoocog8p FUvUvkUYLHD3pxPyE7A== X-Authority-Analysis: v=2.4 cv=RZOgzVtv c=1 sm=1 tr=0 ts=69fe724c cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=SUFyVy6k7XmgMTdL_LUA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: 2XurBl-04zGvPSP6UDhYjY0qkeJ6M-pv X-Proofpoint-ORIG-GUID: 2XurBl-04zGvPSP6UDhYjY0qkeJ6M-pv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080232 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260508_163125_650572_2E6D56ED X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This series adds QMP PCIe PHY support for the Qualcomm Hawi SoC. The Hawi platform features two PCIe PHY configurations: Gen3 x2 and Gen4 x1. The Gen3 x2 PHY uses v10 register definitions, while the Gen4 x1 PHY uses v10.60 register definitions. The series adds: - device tree bindings (patch 1) - v10 register offset headers (patches 2-5) - v10.60 register offset headers (patches 6-9) - driver support with PHY initialization tables for both configurations (patch 10) Overlap: The series has overlap with "phy: qcom: Introduce USB support for Hawi" by Ronak Raheja (see link [1]). Both patch series introduce a subset of v10 registers (this series for PCIe and Ronak's for USB). I have coordinated with Ronak regarding the overlap, and we can update the series to resolve any overlap based on the order of merging. Link: https://lore.kernel.org/all/20260508213234.4643-1-ronak.raheja@oss.qualcomm.com/ [1] Signed-off-by: Matthew Leung --- Matthew Leung (10): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Hawi compatibles phy: qcom-qmp: qserdes-com: Add v10 register offsets phy: qcom-qmp: qserdes-txrx: Add v10 register offsets phy: qcom-qmp: pcs: Add v10 register offsets phy: qcom-qmp: pcs-pcie: Add v10 register offsets phy: qcom-qmp: qserdes-com: Add v10.60 register offsets phy: qcom-qmp: qserdes-txrx: Add v10.60 register offsets phy: qcom-qmp: pcs: Add v10.60 register offsets phy: qcom-qmp: pcs-pcie: Add v10.60 register offsets phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 382 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 + .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h | 23 ++ .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 +++ .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 +++ .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 47 +++ .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h | 109 ++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 10 + 11 files changed, 747 insertions(+) --- base-commit: 17c7841d09ee7d33557fd075562d9289b6018c90 change-id: 20260506-hawi-phy-pcie-283933b4113e Best regards, -- Matthew Leung -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy