From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDC5ACD4F3D for ; Wed, 13 May 2026 18:14:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=S6Ispgr6wUVw9ddDBYk3sYgkAzUbhg6HCc4CJF+YPmE=; b=UpgTNxe/aoX/hG 64T8Qvvwl2VNiglYwr+NHi7HEbGnTKbfsEBzAUIza+yIGpcg8fWprgCRLAVIRwtv3y8EnlJ73r8/j /o2zf1TuLx0Z7Zwb7Os7Jg83cSI8fvvbkGd8rP23gH22BoAhLfT+0E+jp1ezaQpzJjPN7+HnxRpnL Y8oaPXCqfS+DoJtWtp7fdlzzlDj0Ync/eknp8svrBWwOZHmjZZNfGE+pSUBvnFK8ik5JlAPLKIgQK Rk/jlHm5fUnLmR+ewE9fQpUK5fjzcHyYXdjXI1z4NrE485svBUZodC7DA0uT4YM4w9T8Z7yTAsfA+ dz2lOUndtxCpLhtKoMIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wNE69-00000003RX1-2BKA; Wed, 13 May 2026 18:14:21 +0000 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wNE66-00000003RVI-169K for linux-phy@lists.infradead.org; Wed, 13 May 2026 18:14:20 +0000 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64DEd5TW3474786 for ; Wed, 13 May 2026 18:14:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 3o2dYgGq0E5lPn5vU0FBECkmJVwMp6ZZWkBRjZuUung=; b=PXb1bli76W6OLUK6 B/EctDeA7IUNRWW5kS6MN+a8KUVkTnbJIZdRloTzaMnRYwmi935yjV0Op4h8XowJ xRBtPeOIM/IvXV4pvdh2woarzpZtQHmWIw0Lot1ek1FDwlItibqffxrCEqLjrsWV i/dEi6FXTCO/YYgYa6gVnz7rlh7NvEyoNTV9Yb063DxFak8Rs7kcrffse/Jl3cVz RakNe11se/Y+SjLQIkO3DBTVc3K9of2ZHivAI3WCPJE28mZvFabO7ypY5ZB10Q32 tc0bZ4m3eh2qzO/aT90FTjDLQkxRnB+At2R5ES7j3bvlT7+8k5yRPrW50R3rQktG SV28LA== Received: from mail-vs1-f69.google.com (mail-vs1-f69.google.com [209.85.217.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e4p41a7rn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 13 May 2026 18:14:17 +0000 (GMT) Received: by mail-vs1-f69.google.com with SMTP id ada2fe7eead31-632ad092bc5so5838690137.2 for ; Wed, 13 May 2026 11:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778696057; x=1779300857; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3o2dYgGq0E5lPn5vU0FBECkmJVwMp6ZZWkBRjZuUung=; b=BVXkUYW2d+z7ii+AyWE+AQfEmFxoA5dwZKgSeO6qdC79ZxbH84ZxLGOVfkm9y/Di/u bQP8UAgTlb+UEccJH91rVlugbMg3zdhA5uO9D4QVbcMWdk9WFlkpDG0f3rmihLobmHrN dR2yUFeS3VutuZIpw8UuIHrDyqW/npb6e82xgWdZSLu8ichn/HZzkRZTQehvpB28a8Hp ip9n76CGJOLGIaJCqaqpqekVtNGPEhI/cTHnpaeKczyzMG3NE9eM0kW13jRNYPASIgq6 c9nNu5bUSsIjaGAdHTnjv3xNwFSBMXMMQ2S0j3sjimkQduS1wu72SHdJGWecvJQp7XAp 4ZNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778696057; x=1779300857; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3o2dYgGq0E5lPn5vU0FBECkmJVwMp6ZZWkBRjZuUung=; b=kNR5/QK/QXSQoPgeRr/xAnrv04OheR0RYM9fpKrmlyWnGME2F6wyyBKLIJhLxllt8/ ZsCwhUxgXcY8iB19OLeJfr6fC5NqbB6Jxm/D0BNjKxxb7uY+u3Kb9P3rAj/yKwPjOFQ/ rRYnf+QPKMJuLtEaxSCmHVXJT0bGV9UKQEqLsvtvCAqz1CKVhUOTiacoepWaLOoFPq3u MXPVNas1kD3VxfQCCUjyIz/7uX01udegb6ii1geUIy5G/wSs4eSs5ms0huHl/V6fSJG5 MBKXS7XvFp3VRQW15naJ/XSHCXdGcfmmwmKGPjZVWE1c8t2JDzm9B1z3W9P/wDzQ6E5i eLjQ== X-Forwarded-Encrypted: i=1; AFNElJ/yN+YyJ7o2XgEVirKqU8HIEfw0rfO9IYf4TgKdjKUycIrUWAMW4F5ORSEjVqedrNgBtvOoSFtqGRg=@lists.infradead.org X-Gm-Message-State: AOJu0Yx5rmdZudurTlE9+cfQqCED4B/FydNVXIc7R01ji4vY62zijSB1 Ix9nWlH4yG5ka+3rqw7JwD8mMrmG3CzTQ4lgeQ8OgiuERbarxTP8nYY5tuG80ZaX+6pytSCqvwP 12AsBpichKTNUHpB/P3O5lq0LvsDT+6HCzTiHxM8e+/KQvD+wSivDMS5EVQqvZ2hekHNv X-Gm-Gg: Acq92OEotjRa1DLbDoDgakeLP14qSXGsGsh4kensG9DO3xJnsGiNS0Adeuu28g8YoFQ yBCFO54I083wFdgoxWUagO4R7t0Dwv84sVLEnRNf9KUkaIdIa6qxjfI35Ik9vdfEuDeXbFmcSxI KDkPAJeAFzugnHE+08LGOUhvA+R372ezxNTGgLO+5JME5ajk7g3GgjSbCzOYif65y9rrAB21Sl7 8C51I4Bl1w3h7+IF3MgEdtYZ6PXDafWSh6ZTBNI7RRLapg+XdZ+pTURE9nj6EQ2Axf7exfbE8iL S5Gob+YuK9U0GrvtQfgrCqmwcNEQKFz6vD1uBYPbdyuBgYvMoOo73IXH/v8Ne5aUYgB+fO40W7W Mx2eAt0pbkJRmUeTAZyqEIYRPz+PgsBFVnWovqUGGMnpXgHChx6GO6TgQSHH2IsLzo5ebztoSeW 0x7CJirXMdowjLMcSMuDHOoxyKwGO8CDWMD0bJ2OwPOlQb9g== X-Received: by 2002:a67:e703:0:b0:632:78bc:2bdf with SMTP id ada2fe7eead31-637ab388366mr2362452137.31.1778696056641; Wed, 13 May 2026 11:14:16 -0700 (PDT) X-Received: by 2002:a67:e703:0:b0:632:78bc:2bdf with SMTP id ada2fe7eead31-637ab388366mr2362417137.31.1778696056073; Wed, 13 May 2026 11:14:16 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a8bd7d8974sm3174770e87.64.2026.05.13.11.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 11:14:15 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 13 May 2026 21:14:08 +0300 Subject: [PATCH v9 5/5] phy: qualcomm: add MSM8974 HDMI PHY support MIME-Version: 1.0 Message-Id: <20260513-fd-hdmi-phy-v9-5-ca98c72f1f9f@oss.qualcomm.com> References: <20260513-fd-hdmi-phy-v9-0-ca98c72f1f9f@oss.qualcomm.com> In-Reply-To: <20260513-fd-hdmi-phy-v9-0-ca98c72f1f9f@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Neil Armstrong Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-phy@lists.infradead.org, Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=10299; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=fiAxSKr0MiXtgdMoguQGBGHvUIsEFSFdo1fVWLdz2eA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqBL9t2xJILDiTUglQXAPwOJoAblLE9eTWuCWxM UG7ow3AGp6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCagS/bQAKCRCLPIo+Aiko 1YR1B/44Qhu2PZRI2XldEMpcilSgnWABIFpUPMlVRyggw/TwqvHsEJkI/Y2Delv9Zpv5/wooIeH ksgXuJeIrM8I+/5MWjCXRpcczv0rAxiHZby9NojAzo2kIWbxJoi/3GrhTylYoDFeXXLK0HDEIEO ZlyVyonGAx4O8WW7psKY7yUXxMOQ1843A8Inth3mNIkC10m274Jhoakc9jCWGt7i0sTLrcn5Uz0 sVYvDSW/vpnKQQsoSOdDm8KAizpItql6lGSIkm6JOOyTGcQC8vdEu9Vo3mGeAZj2nT+aqZWi6n/ TEXqqRd0CaTU675gqmbeDi7rVNZBeVdeatN1kzNEjUj+/E/3 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=df+wG3Xe c=1 sm=1 tr=0 ts=6a04bf79 cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=U0NZ41NzsMKYcVuMMSoA:9 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE4MiBTYWx0ZWRfXydk0s9kWowD+ XLZBB+v4v1Em3JEEoVZXlBAxf+z4b4x0WTLQ3bLLIlU5eXeAyOjOtiKhBZCljva/dbdOSBmpS+8 Ed+rWxtnl3B5yGTwZ271M7oRHpiKZCezs5pLwQYHrpgXNrIqTfLptRjRucu5glTXiwXrwiyx6S0 pVFOwWouYVrWtCfbQOi+sl2BRplgDA6JXeujVeOEJjDtAIctUTor9gg9hnHtxYERRGswm5O2Hjs A9mnMNmpe9bE7Zkh3i36vYvVUzEWJKQUQAtFy3t1P0oDamv4qSDrqZD2m5odMCQbbEjsPfIk7fC vauSY9ptDvjKGHyykovMdy6YbGr1rN+h7C6Sxv3irdeByRXeCa0aUOkSYKOZBMLLk6o2+rx4oKq XfXvL2ANjwn+q5MA4BPPYZXtekBcQE6xck9ykRBkggz5ZzHe2zQmVCsp3U7MfXcsSRdvbn81G3o Ss9zhWcQkSn7X/L04rg== X-Proofpoint-GUID: SzBIxkntIycxu2Ed21QJzeIqPR0g92kU X-Proofpoint-ORIG-GUID: SzBIxkntIycxu2Ed21QJzeIqPR0g92kU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_02,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130182 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260513_111419_450111_01506487 X-CRM114-Status: GOOD ( 18.12 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add support for HDMI PHY on Qualcomm MSM8974 / APQ8074 platforms. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c | 282 +++++++++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c b/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c index 720757f8f393..7d398060b3a3 100644 --- a/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c +++ b/drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c @@ -6,10 +6,13 @@ * Author: Rob Clark */ +#include #include #include +#include #include "phy-qcom-hdmi-preqmp.h" +#include "phy-qcom-uniphy.h" #define REG_HDMI_8x74_ANA_CFG0 0x00000000 #define REG_HDMI_8x74_ANA_CFG1 0x00000004 @@ -31,8 +34,282 @@ #define REG_HDMI_8x74_BIST_PATN3 0x00000048 #define REG_HDMI_8x74_STATUS 0x0000005c +#define HDMI_8974_VCO_MAX_FREQ 1800000000UL +#define HDMI_8974_VCO_MIN_FREQ 600000000UL + +#define HDMI_8974_COMMON_DIV 5 + +static inline void write16(u16 val, void __iomem *reg) +{ + writel(val & 0xff, reg); + writel(val >> 8, reg + 4); +} + +static inline void write24(u32 val, void __iomem *reg) +{ + writel(val & 0xff, reg); + writel((val >> 8) & 0xff, reg + 4); + writel(val >> 16, reg + 8); +} + +static inline u32 read24(void __iomem *reg) +{ + u32 val = readl(reg); + + val |= readl(reg + 4) << 8; + val |= readl(reg + 8) << 16; + + return val; +} + +static void qcom_uniphy_setup(void __iomem *base, unsigned int ref_freq, + bool sdm_mode, + bool ref_freq_mult_2, + bool dither, + unsigned int refclk_div, + unsigned int vco_freq) +{ + unsigned int int_ref_freq = ref_freq * (ref_freq_mult_2 ? 2 : 1); + unsigned int div_in_freq = vco_freq / refclk_div; + unsigned int dc_offset = div_in_freq / int_ref_freq - 1; + unsigned int sdm_freq_seed; + unsigned int val; + u64 tmp = div_in_freq % int_ref_freq; + + tmp *= 0x10000; + sdm_freq_seed = div_u64(tmp, int_ref_freq); + + val = FIELD_PREP(UNIPHY_PLL_REFCLK_DBLR, ref_freq_mult_2) | + FIELD_PREP(UNIPHY_PLL_REFCLK_DIV, refclk_div - 1); + writel(val, base + UNIPHY_PLL_REFCLK_CFG); + + if (sdm_mode) { + writel(0, base + UNIPHY_PLL_SDM_CFG0); + writel(FIELD_PREP(UNIPHY_PLL_SDM_DITHER_EN, dither) | dc_offset, + base + UNIPHY_PLL_SDM_CFG1); + write24(sdm_freq_seed, base + UNIPHY_PLL_SDM_CFG2); + } else { + writel(UNIPHY_PLL_SDM_BYP | dc_offset, base + UNIPHY_PLL_SDM_CFG0); + writel(0, base + UNIPHY_PLL_SDM_CFG1); + write24(0, base + UNIPHY_PLL_SDM_CFG2); + } + + write16(mult_frac(ref_freq, 5, 1000000), base + UNIPHY_PLL_CAL_CFG8); + write16(vco_freq / 16, base + UNIPHY_PLL_CAL_CFG10); +} + +static unsigned long qcom_uniphy_recalc(void __iomem *base, unsigned long parent_rate) +{ + unsigned long rate; + u32 refclk_cfg; + u32 dc_offset; + u64 fraq_n; + u32 val; + + refclk_cfg = readl(base + UNIPHY_PLL_REFCLK_CFG); + if (refclk_cfg & UNIPHY_PLL_REFCLK_DBLR) + parent_rate *= 2; + + val = readl(base + UNIPHY_PLL_SDM_CFG0); + if (FIELD_GET(UNIPHY_PLL_SDM_BYP, val)) { + dc_offset = FIELD_GET(UNIPHY_PLL_SDM_BYP_DIV, val); + fraq_n = 0; + } else { + dc_offset = FIELD_GET(UNIPHY_PLL_SDM_DC_OFFSET, + readl(base + UNIPHY_PLL_SDM_CFG1)); + fraq_n = read24(base + UNIPHY_PLL_SDM_CFG2); + } + + rate = (dc_offset + 1) * parent_rate; + rate += div_u64(fraq_n * parent_rate, 0x10000); + + rate *= FIELD_GET(UNIPHY_PLL_REFCLK_DIV, refclk_cfg) + 1; + + return rate; +} + +static const unsigned int qcom_hdmi_8974_divs[] = {1, 2, 4, 6}; + +static unsigned long qcom_hdmi_8974_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct qcom_hdmi_preqmp_phy *hdmi_phy = hw_clk_to_phy(hw); + u32 div_idx = readl(hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV1_CFG); + unsigned long rate = qcom_uniphy_recalc(hdmi_phy->pll_reg, parent_rate); + + return rate / HDMI_8974_COMMON_DIV / qcom_hdmi_8974_divs[div_idx & 0x3]; +} + +static int qcom_hdmi_8974_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long min_freq = HDMI_8974_VCO_MIN_FREQ / HDMI_8974_COMMON_DIV; + unsigned long max_freq = HDMI_8974_VCO_MAX_FREQ / HDMI_8974_COMMON_DIV; + + req->rate = clamp(req->rate, min_freq / 6, max_freq); + + return 0; +} + +static const struct clk_ops qcom_hdmi_8974_pll_ops = { + .recalc_rate = qcom_hdmi_8974_pll_recalc_rate, + .determine_rate = qcom_hdmi_8974_pll_determine_rate, +}; + +static int qcom_hdmi_msm8974_phy_find_div(unsigned long long pixclk) +{ + unsigned long long min_freq = HDMI_8974_VCO_MIN_FREQ / HDMI_8974_COMMON_DIV; + int i; + + if (pixclk > HDMI_8974_VCO_MAX_FREQ / HDMI_8974_COMMON_DIV) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(qcom_hdmi_8974_divs); i++) { + if (pixclk >= min_freq / qcom_hdmi_8974_divs[i]) + return i; + } + + return -EINVAL; +} + +static int qcom_hdmi_msm8974_phy_pll_set_rate(struct qcom_hdmi_preqmp_phy *hdmi_phy) +{ + unsigned long long pixclk = hdmi_phy->hdmi_opts.tmds_char_rate; + unsigned long vco_rate; + unsigned int div; + int div_idx = 0; + + div_idx = qcom_hdmi_msm8974_phy_find_div(pixclk); + if (WARN_ON(div_idx < 0)) + return div_idx; + + div = qcom_hdmi_8974_divs[div_idx]; + vco_rate = pixclk * HDMI_8974_COMMON_DIV * div; + + writel(0x81, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + writel(0x19, hdmi_phy->pll_reg + UNIPHY_PLL_VCOLPF_CFG); + writel(0x0e, hdmi_phy->pll_reg + UNIPHY_PLL_LPFR_CFG); + writel(0x20, hdmi_phy->pll_reg + UNIPHY_PLL_LPFC1_CFG); + writel(0x0d, hdmi_phy->pll_reg + UNIPHY_PLL_LPFC2_CFG); + + qcom_uniphy_setup(hdmi_phy->pll_reg, 19200000, true, true, true, 1, vco_rate); + + writel(0x10, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG0); + writel(0x1a, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG1); + writel(0x05, hdmi_phy->pll_reg + UNIPHY_PLL_LKDET_CFG2); + + writel(div_idx, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV1_CFG); + + writel(0x00, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV2_CFG); + writel(0x00, hdmi_phy->pll_reg + UNIPHY_PLL_POSTDIV3_CFG); + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_CAL_CFG2); + + writel(0x1f, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); + udelay(50); + + writel(0x0f, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL1); + writel(0x10, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0xdb, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG0); + writel(0x43, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG1); + if (pixclk == 297000000) { + writel(0x06, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x03, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } else if (pixclk == 268500000) { + writel(0x05, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } else { + writel(0x02, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG2); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG3); + } + + writel(0x04, hdmi_phy->pll_reg + UNIPHY_PLL_VREG_CFG); + + writel(0xd0, hdmi_phy->phy_reg + REG_HDMI_8x74_DCC_CFG0); + writel(0x1a, hdmi_phy->phy_reg + REG_HDMI_8x74_DCC_CFG1); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG0); + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG1); + + if (pixclk == 268500000) + writel(0x11, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG2); + else + writel(0x02, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG2); + + writel(0x05, hdmi_phy->phy_reg + REG_HDMI_8x74_TXCAL_CFG3); + udelay(200); + + return 0; +} + +static int qcom_hdmi_msm8974_phy_pll_enable(struct qcom_hdmi_preqmp_phy *hdmi_phy) +{ + int ret; + unsigned long status; + + /* Global enable */ + writel(0x81, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + /* Power up power gen */ + writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); + udelay(350); + + /* PLL power up */ + writel(0x01, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + + /* Power up PLL LDO */ + writel(0x03, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(350); + + /* PLL power up */ + writel(0x0f, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(350); + + /* Poll for PLL ready status */ + ret = readl_poll_timeout(hdmi_phy->pll_reg + UNIPHY_PLL_STATUS, + status, status & UNIPHY_PLL_LOCK, + 100, 2000); + if (ret) { + dev_warn(hdmi_phy->dev, "HDMI PLL not ready\n"); + goto err; + } + + udelay(350); + + /* Poll for PHY ready status */ + ret = readl_poll_timeout(hdmi_phy->phy_reg + REG_HDMI_8x74_STATUS, + status, status & BIT(0), + 100, 2000); + if (ret) { + dev_warn(hdmi_phy->dev, "HDMI PHY not ready\n"); + goto err; + } + + return 0; + +err: + writel(0, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + writel(0, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + + return ret; +} + static int qcom_hdmi_msm8974_phy_power_on(struct qcom_hdmi_preqmp_phy *hdmi_phy) { + int ret; + + ret = qcom_hdmi_msm8974_phy_pll_set_rate(hdmi_phy); + if (ret) + return ret; + + ret = qcom_hdmi_msm8974_phy_pll_enable(hdmi_phy); + if (ret) + return ret; + writel(0x1b, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG0); writel(0xf2, hdmi_phy->phy_reg + REG_HDMI_8x74_ANA_CFG1); writel(0x00, hdmi_phy->phy_reg + REG_HDMI_8x74_BIST_CFG0); @@ -49,6 +326,10 @@ static int qcom_hdmi_msm8974_phy_power_off(struct qcom_hdmi_preqmp_phy *hdmi_phy { writel(0x7f, hdmi_phy->phy_reg + REG_HDMI_8x74_PD_CTRL0); + writel(0, hdmi_phy->pll_reg + UNIPHY_PLL_GLB_CFG); + udelay(5); + writel(0, hdmi_phy->phy_reg + REG_HDMI_8x74_GLB_CFG); + return 0; } @@ -67,5 +348,6 @@ const struct qcom_hdmi_preqmp_cfg msm8974_hdmi_phy_cfg = { .power_on = qcom_hdmi_msm8974_phy_power_on, .power_off = qcom_hdmi_msm8974_phy_power_off, + .pll_ops = &qcom_hdmi_8974_pll_ops, .pll_parent = &msm8974_hdmi_pll_parent, }; -- 2.47.3 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy