Re: [PATCH] phy: ti-pipe3: Fix clock leak in init error path

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] ti_pipe3_init() completely ignores the return value of ti_pipe3_enable_clocks(), leading to unclocked hardware access and unbalanced clock disables.
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commit 6e3b53b5ea9af504f2a62f9abfc933bbbb671e25
Author: Hongling Zeng <zenghongling@kylinos.cn>

phy: ti-pipe3: Fix clock leak in init error path

This commit adds a clock cleanup in the PCIe error path of ti_pipe3_init()
to prevent clocks from being permanently enabled when regmap_update_bits()
fails.

Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@smtp.kernel.org/

> diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
> index b5543b5c674c8..b5ee0af77c9f6 100644
> --- a/drivers/phy/ti/phy-ti-pipe3.c
> +++ b/drivers/phy/ti/phy-ti-pipe3.c
> @@ -515,6 +515,8 @@ static int ti_pipe3_init(struct phy *x)
>  		val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
>  		ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
>  					 PCIE_PCS_MASK, val);
> +		if (ret)
> +			ti_pipe3_disable_clocks(phy);

Could this error path trigger an unbalanced clock disable warning if the clocks
were never successfully enabled?

Earlier in ti_pipe3_init(), the return value of ti_pipe3_enable_clocks() is
ignored:

drivers/phy/ti/phy-ti-pipe3.c:ti_pipe3_init() {
        ...
        int ret = 0;

        ti_pipe3_enable_clocks(phy);
        /*
         * Set pcie_pcs register to 0x96 for proper functioning of phy
        ...
}

If ti_pipe3_enable_clocks() fails, it rolls back and cleanly disables any
partially enabled clocks.

The initialization then continues anyway, interacting with unclocked hardware,
which might cause a bus error.

If it reaches this new error path because regmap_update_bits() fails,
ti_pipe3_disable_clocks() will be called unconditionally on already-disabled
clocks.

>  		return ret;
>  	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260518035105.26607-1-zenghongling@kylinos.cn?part=1

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