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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36f70a29cd6sm2483385a91.11.2026.06.04.03.12.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2026 03:12:30 -0700 (PDT) From: Joey Lu To: Vinod Koul , Neil Armstrong Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jacky Huang , Shan-Chun Hung , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 1/2] dt-bindings: phy: nuvoton: Add MA35D1 USB2 OTG PHY binding Date: Thu, 4 Jun 2026 18:12:19 +0800 Message-ID: <20260604101220.1092822-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260604101220.1092822-1-a0987203069@gmail.com> References: <20260604101220.1092822-1-a0987203069@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260604_031232_017846_997E6C9B X-CRM114-Status: GOOD ( 15.70 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add device tree binding documentation for the Nuvoton MA35D1 USB 2.0 OTG PHY driver (nuvoton,ma35d1-usb2-phy-otg). PHY index 0 (USB0) is an OTG port whose signals are routed by a hardware mux to either the DWC2 device controller or the EHCI0/OHCI0 host controllers depending on the USB ID pin state. PHY index 1 (USB1) is a dedicated host-only port. Optional properties allow board-specific resistor calibration trim (nuvoton,rcalcode) and over-current detect polarity configuration (nuvoton,oc-active-high). Signed-off-by: Joey Lu --- .../phy/nuvoton,ma35d1-usb2-phy-otg.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy-otg.yaml diff --git a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy-otg.yaml b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy-otg.yaml new file mode 100644 index 000000000000..19f074565cc6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy-otg.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nuvoton,ma35d1-usb2-phy-otg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 USB 2.0 host PHY + +maintainers: + - Joey Lu + +description: + USB 2.0 PHY driver for the Nuvoton MA35D1 SoC, used by the EHCI and + OHCI host controllers. + + USB0 (PHY index 0) is an OTG port whose physical signals are routed to + either the DWC2 device controller or the EHCI0/OHCI0 host controller by + a hardware mux that follows the USB ID pin. + + USB1 (PHY index 1) is a dedicated host port with no OTG capability. + +properties: + compatible: + const: nuvoton,ma35d1-usb2-phy-otg + + clocks: + maxItems: 1 + + nuvoton,sys: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the system management syscon. + - description: PHY instance index. + enum: + - 0 # USB0, OTG port (shared with DWC2 gadget controller) + - 1 # USB1, host-only port + description: + A phandle to the syscon node covering the SYS register block, with + one argument selecting the PHY instance. Index 0 selects the OTG + port PHY (USB0) and index 1 selects the host-only PHY (USB1). + + "#phy-cells": + const: 0 + + nuvoton,rcalcode: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Resistor calibration trim code written to the RCALCODE field in + USBPMISCR. The 4-bit value adjusts the PHY's internal termination + resistance. When absent the hardware reset default is used. + + nuvoton,oc-active-high: + type: boolean + description: + When present, the over-current detect input from the VBUS power + switch is treated as active-high. The default (property absent) is + active-low. This setting is shared by both USB host ports. + +required: + - compatible + - clocks + - nuvoton,sys + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + usb_hphy0: usb-host-phy { + compatible = "nuvoton,ma35d1-usb2-phy-otg"; + clocks = <&clk HUSBH0_GATE>; + nuvoton,sys = <&sys 0>; + #phy-cells = <0>; + }; -- 2.43.0 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy