Re: [PATCH 3/8] arm64: dts: qcom: sm8450: Modify GPU operating points - sashiko-bot

From: sashiko-bot@kernel.org
To: "Esteban Urrutia via B4 Relay" <devnull+esteuwu.proton.me@kernel.org>
Cc: devicetree@vger.kernel.org, robh@kernel.org,
	neil.armstrong@linaro.org, vkoul@kernel.org, conor+dt@kernel.org,
	olteanv@gmail.com, linux-phy@lists.infradead.org
Subject: Re: [PATCH 3/8] arm64: dts: qcom: sm8450: Modify GPU operating points
Date: Tue, 23 Jun 2026 01:10:38 +0000	[thread overview]
Message-ID: <20260623011038.AFA271F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260622-sm8450-qol-v1-3-37e2ee8df9da@proton.me>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Removing the 3 lowest GPU OPPs breaks the 1:1 index mapping between the GPU frequency table and the hardcoded GMU bandwidth table in the Adreno DRM driver, causing severe memory bandwidth starvation at high GPU frequencies.
--

commit d0ec9d0cbceaf15f2295a4c6a613a8ca7a354eea
Author: Esteban Urrutia <esteuwu@proton.me>

arm64: dts: qcom: sm8450: Modify GPU operating points

This commit removes the 317MHz, 285MHz, and 220MHz GPU operating points from
the SM8450 device tree, as they do not exist in the downstream device trees.

> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index e34e3c05bf74c..5e331a25e22a2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2495,21 +2495,6 @@ opp-350000000 {
>  					opp-hz = /bits/ 64 <350000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>  				};
> -
> -				opp-317000000 {
> -					opp-hz = /bits/ 64 <317000000>;
> -					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> -				};

[Severity: High]
Will removing these 3 lowest GPU OPPs break the index mapping between the
GPU frequency table and the GMU bandwidth table in the Adreno driver?

The Adreno A730 driver doesn't use dynamic bandwidth voting. Instead, it
sends a hardcoded table of exactly 12 memory bandwidth levels to the GMU
firmware:

drivers/gpu/drm/msm/adreno/a6xx_hfi.c:a730_build_bw_table() {
    ...
    msg->bw_level_num = 12;
    ...
}

The GMU firmware applies the bandwidth vote corresponding to the GPU
performance level index. Previously, with 12 GPU OPPs, the maximum frequency
mapped to the maximum bandwidth at index 11.

By removing 3 OPPs here, the active OPPs are reduced to 9. Does this mean the
maximum frequency of 818MHz will now map to performance index 8 instead?

If so, this would cause the GMU to apply the lower bandwidth vote from index 8
when the GPU is at maximum frequency, severely reducing the available memory
bandwidth and bottlenecking the GPU under heavy load.

> -
> -				opp-285000000 {
> -					opp-hz = /bits/ 64 <285000000>;
> -					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> -				};
> -
> -				opp-220000000 {
> -					opp-hz = /bits/ 64 <220000000>;
> -					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> -				};
>  			};
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-sm8450-qol-v1-0-37e2ee8df9da@proton.me?part=3

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