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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f64dc839sm8538545ad.68.2026.06.24.19.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2026 19:40:11 -0700 (PDT) From: Joey Lu To: Vinod Koul , Neil Armstrong Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Catalin Marinas , Jacky Huang , Shan-Chun Hung , Hui-Ping Chen , Joey Lu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 2/4] dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port OTG support Date: Thu, 25 Jun 2026 10:39:56 +0800 Message-ID: <20260625023958.569299-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260625023958.569299-1-a0987203069@gmail.com> References: <20260625023958.569299-1-a0987203069@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260624_194013_432571_1A48B00C X-CRM114-Status: GOOD ( 15.83 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The MA35D1 has two USB PHY ports managed by the same hardware block: - PHY0 (index 0): OTG port shared between the DWC2 gadget controller and EHCI0/OHCI0 host controllers. A hardware mux follows the USB ID pin automatically. - PHY1 (index 1): dedicated host-only port for EHCI1/OHCI1. Extend the existing binding to cover both ports: - The PHY node is now a child of the system-management syscon node with a reg property. The nuvoton,sys phandle and clocks properties are removed; the driver derives the regmap from its parent, and clock gating is owned by each individual USB controller. - #phy-cells changes from 0 to 1: the cell selects the PHY port. - Two optional board-tuning properties are added: nuvoton,rcalcode for per-port resistor trim and nuvoton,oc-active-high for over-current polarity. Signed-off-by: Joey Lu --- .../bindings/phy/nuvoton,ma35d1-usb2-phy.yaml | 62 ++++++++++++++----- 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml index fff858c909a0..a20d03c80932 100644 --- a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml @@ -8,38 +8,72 @@ title: Nuvoton MA35D1 USB2 phy maintainers: - Hui-Ping Chen + - Joey Lu + +description: + USB 2.0 PHY for the Nuvoton MA35D1 SoC. The PHY node is a child of the + system-management syscon node and covers both PHY ports. + + PHY0 (index 0) is the OTG port whose signals are routed to either the DWC2 + gadget controller or the EHCI0/OHCI0 host controller by a hardware mux that + follows the USB ID pin automatically. + + PHY1 (index 1) is a dedicated host-only port used by EHCI1/OHCI1. properties: compatible: enum: - nuvoton,ma35d1-usb2-phy + reg: + maxItems: 1 + "#phy-cells": - const: 0 + const: 1 + description: + The single cell selects the PHY port. 0 selects the OTG port (USB0, + shared with DWC2 gadget controller) and 1 selects the host-only port + (USB1). - clocks: - maxItems: 1 + nuvoton,rcalcode: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 15 + description: + Resistor calibration trim codes for PHY0 and PHY1 respectively. + Each 4-bit value is written to the RCALCODE field in USBPMISCR and + adjusts the PHY's internal termination resistance. Both entries are + optional; when absent the hardware reset default is used. - nuvoton,sys: - $ref: /schemas/types.yaml#/definitions/phandle + nuvoton,oc-active-high: + type: boolean description: - phandle to syscon for checking the PHY clock status. + When present, the over-current detect input from the VBUS power switch + is treated as active-high. The default (property absent) is active-low. + This setting is shared by both USB host ports. required: - compatible + - reg - "#phy-cells" - - clocks - - nuvoton,sys additionalProperties: false examples: - | - #include + system-management@40460000 { + compatible = "nuvoton,ma35d1-reset", "syscon", "simple-mfd"; + reg = <0x40460000 0x200>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; - usb_phy: usb-phy { - compatible = "nuvoton,ma35d1-usb2-phy"; - clocks = <&clk USBD_GATE>; - nuvoton,sys = <&sys>; - #phy-cells = <0>; + usb-phy@60 { + compatible = "nuvoton,ma35d1-usb2-phy"; + reg = <0x60 0x14>; + #phy-cells = <1>; + }; }; -- 2.43.0 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy