Re: [PATCH 6/8] phy: tegra: xusb: Add Tegra264 support - sashiko-bot

From: sashiko-bot@kernel.org
To: "Wayne Chang" <waynec@nvidia.com>
Cc: olteanv@gmail.com, vkoul@kernel.org, conor+dt@kernel.org,
	neil.armstrong@linaro.org, linux-phy@lists.infradead.org,
	robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 6/8] phy: tegra: xusb: Add Tegra264 support
Date: Mon, 29 Jun 2026 09:45:25 +0000	[thread overview]
Message-ID: <20260629094525.D07981F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260629093406.1118594-7-waynec@nvidia.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing `.has_per_pad_term = true` for `tegra264_xusb_padctl_soc` leads to incorrect USB2 PHY termination calibration.
- [Low] Missing prototype compiler warning for `tegra264_xusb_padctl_soc` when its specific config is disabled.
--

commit 22b0fd28aa94a55231606c8cbbf28effe50f3f35
Author: Wayne Chang <waynec@nvidia.com>

phy: tegra: xusb: Add Tegra264 support

Add support for the XUSB pad controller for Tegra264. Most of the Tegra264
XUSB PADCTL registers definition and programming sequence are the same as
Tegra234, and they can share the same driver.

> diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
> index 9c1bcd4a72ac6..3eb60ed09b687 100644
> --- a/drivers/phy/tegra/xusb-tegra186.c
> +++ b/drivers/phy/tegra/xusb-tegra186.c
[ ... ]
> @@ -1753,6 +1754,29 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
>  	.has_per_pad_term = true,
>  };
>  EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
> +
> +const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc = {
> +	.num_pads = ARRAY_SIZE(tegra194_pads),
> +	.pads = tegra194_pads,
> +	.ports = {
> +		.usb2 = {
> +			.ops = &tegra186_usb2_port_ops,
> +			.count = 4,
> +		},
> +		.usb3 = {
> +			.ops = &tegra186_usb3_port_ops,
> +			.count = 4,
> +		},
> +	},
> +	.ops = &tegra186_xusb_padctl_ops,
> +	.supply_names = tegra194_xusb_padctl_supply_names,
> +	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
> +	.supports_gen2 = true,
> +	.poll_trk_completed = true,
> +	.trk_hw_mode = true,
> +	.supports_lp_cfg_en = true,
> +};

[Severity: Medium]
Since the commit message states Tegra264 shares the same programming sequence
as Tegra234, should this struct also include .has_per_pad_term = true?

Without this flag, tegra186_xusb_read_fuse_calibration() will default to
copying pad 0's calibration to pads 1-3 instead of reading their specific
hardware values.

> +EXPORT_SYMBOL_GPL(tegra264_xusb_padctl_soc);
>  #endif
>  
>  MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");

[ ... ]

> diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
> index 77609e54de66a..d8d799d9e7522 100644
> --- a/drivers/phy/tegra/xusb.h
> +++ b/drivers/phy/tegra/xusb.h
> @@ -514,5 +514,8 @@ extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
>  #if defined(CONFIG_ARCH_TEGRA_234_SOC)
>  extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc;
>  #endif
> +#if defined(CONFIG_ARCH_TEGRA_264_SOC)
> +extern const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc;
> +#endif

[Severity: Low]
Does this create a missing prototype warning (-Wmissing-prototypes) when
building with CONFIG_ARCH_TEGRA_194_SOC=y but CONFIG_ARCH_TEGRA_264_SOC=n?

In xusb-tegra186.c, tegra264_xusb_padctl_soc is defined unconditionally if
any of the 194, 234, or 264 configs are enabled. However, the extern
declaration here in xusb.h is only visible if CONFIG_ARCH_TEGRA_264_SOC is set.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629093406.1118594-1-waynec@nvidia.com?part=6

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