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From: sashiko-bot@kernel.org
To: "Esteban Urrutia" <esteuwu@proton.me>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	conor+dt@kernel.org, olteanv@gmail.com, vkoul@kernel.org,
	robh@kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH 6/6] phy: qcom: qmp-combo: Add SM8475 support
Date: Tue, 14 Jul 2026 06:47:15 +0000	[thread overview]
Message-ID: <20260714064715.86D1D1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260714-sm8475-bup-v1-6-b2871be2b4ec@proton.me>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing .calibrate_dp_phy callback in sm8475_usb3dpphy_cfg breaks AUX channel tuning
--

--- Patch [6]: [PATCH 6/6] phy: qcom: qmp-combo: Add SM8475 support ---
commit e78dfb3ee5c0edb9f6e26900169472c958e036c0
Author: Esteban Urrutia <esteuwu@proton.me>

phy: qcom: qmp-combo: Add SM8475 support

This commit adds QMP combo PHY support for the Qualcomm SM8475 SoC. It
introduces RX and PCS USB tables while reusing SERDES, TX, and PCS tables
from other SoCs to support USB Type-C and DP Alt Mode.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 8c09d4c1594d0..2a58a1c3cb640 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

[ ... ]

> @@ -2916,6 +2965,51 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
>  	.has_pwrdn_delay	= true,
>  };
>  
> +static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = {
> +	.offsets		= &qmp_combo_offsets_v3,
> +
> +	.serdes_tbl		= sar2130p_usb3_serdes_tbl,

[ ... ]

> +	.dp_aux_init		= qmp_v4_dp_aux_init,
> +	.configure_dp_tx	= qmp_v4_configure_dp_tx,
> +	.configure_dp_clocks	= qmp_v3_configure_dp_clocks,
> +	.configure_dp_phy	= qmp_v4_configure_dp_phy,

[Severity: Medium]
Is the calibrate_dp_phy callback intentionally omitted from this
configuration?

Looking at the other QMP combo PHY configurations in this driver, such as
sm8350_usb3dpphy_cfg and sm8550_usb3dpphy_cfg, they all include this
callback, typically set to qmp_v4_calibrate_dp_phy.

If it is missing, when an external DP monitor requires non-default AUX swing
values, the DRM DP driver's link training retry loop will call
phy_calibrate(). Because calibrate_dp_phy is NULL, this will silently return
0 without writing the new settings, causing the DP retry loop to get stuck
using the same failing initial hardware parameters.

> +
> +	.regs			= qmp_v6_usb3phy_regs_layout,
> +	.reset_list		= msm8996_usb3phy_reset_l,
> +	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
> +	.vreg_list		= qmp_phy_vreg_l,
> +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me?part=6

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

      reply	other threads:[~2026-07-14  6:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-14  6:36 [PATCH 0/6] Initial PCIe0 and QMP USB PHYs support for SM8475 Esteban Urrutia via B4 Relay
2026-07-14  6:36 ` [PATCH 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY Esteban Urrutia via B4 Relay
2026-07-14  6:43   ` sashiko-bot
2026-07-14  6:36 ` [PATCH 2/6] phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets Esteban Urrutia via B4 Relay
2026-07-14  6:53   ` sashiko-bot
2026-07-14  6:36 ` [PATCH 3/6] phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port Esteban Urrutia via B4 Relay
2026-07-14  6:36 ` [PATCH 4/6] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY Esteban Urrutia via B4 Relay
2026-07-14  6:47   ` sashiko-bot
2026-07-14  6:36 ` [PATCH 5/6] phy: qcom: qmp-combo: Add serdes and RBR/HBR/HBR2/HBR3 tables for v1 DP PLLs Esteban Urrutia via B4 Relay
2026-07-14  6:49   ` sashiko-bot
2026-07-14  6:36 ` [PATCH 6/6] phy: qcom: qmp-combo: Add SM8475 support Esteban Urrutia via B4 Relay
2026-07-14  6:47   ` sashiko-bot [this message]

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