From: sashiko-bot@kernel.org
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: olteanv@gmail.com, linux-phy@lists.infradead.org,
conor+dt@kernel.org, neil.armstrong@linaro.org, vkoul@kernel.org,
devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY
Date: Mon, 20 Jul 2026 14:01:46 +0000 [thread overview]
Message-ID: <20260720140147.363571F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260720135344.84183-2-angelogioacchino.delregno@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Typo in the device tree binding description listing an invalid PCIe link rate (6.0 GT/s instead of 8.0 GT/s).
--
--- Patch [1]: [PATCH v2 1/2] dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY ---
commit 44ee552d23d168aeb37986df1a94ba1101ff1252
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY
This commit adds device tree bindings for the MT8196 MediaTek PCI-Express
Gen4 S-PHY. It documents the capabilities, register spaces, and required
properties for this PHY.
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml
> new file mode 100644
> index 0000000000000..c24871f7e0e5a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml
> @@ -0,0 +1,93 @@
[ ... ]
> +description:
> + The MediaTek PCI-Express Gen4 S-PHY is capable of data serialization
> + and de-serialization with 8, 10, 128 or 130 bits (16GT/s) encoding
> + and decoding, has analog buffers, elastic buffers and mechanisms for
> + receiver detection.
> + This PHY supports link rates of 2.5, 5.0, 6.0 and 16.0 GT/s per-lane
^^^
[Severity: Low]
This isn't a bug, but is 6.0 GT/s a typo for 8.0 GT/s here?
Standard PCIe link rates are typically 2.5, 5.0, 8.0 (Gen3), and 16.0 GT/s,
while 6.0 GT/s is a rate usually associated with SATA rather than PCIe.
> + in both Root Complex (RC) and End Point (EP) modes, depending on the
> + chosen port.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720135344.84183-1-angelogioacchino.delregno@collabora.com?part=1
--
linux-phy mailing list
linux-phy@lists.infradead.org
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next prev parent reply other threads:[~2026-07-20 14:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 13:53 [PATCH v2 0/2] PHY: Add MediaTek PCI-Express Gen4 S-PHY Driver AngeloGioacchino Del Regno
2026-07-20 13:53 ` [PATCH v2 1/2] dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY AngeloGioacchino Del Regno
2026-07-20 14:01 ` sashiko-bot [this message]
2026-07-20 13:53 ` [PATCH v2 2/2] phy: mediatek: Add support for " AngeloGioacchino Del Regno
2026-07-20 14:13 ` sashiko-bot
2026-07-20 15:19 ` AngeloGioacchino Del Regno
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