From: sashiko-bot@kernel.org
To: "Esteban Urrutia" <esteuwu@proton.me>
Cc: devicetree@vger.kernel.org, olteanv@gmail.com,
neil.armstrong@linaro.org, vkoul@kernel.org,
linux-phy@lists.infradead.org, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v3 2/2] phy: qcom: qmp-combo: Add SM8475 support
Date: Thu, 23 Jul 2026 02:11:43 +0000 [thread overview]
Message-ID: <20260723021143.8B7401F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260722-sm8475-bup-usbss-v3-2-0dd5da218ab2@proton.me>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `sm8475_usb3dpphy_cfg` structure is missing the `.calibrate_dp_phy` callback assignment, which is required for robust DisplayPort link training.
--
--- Patch [2]: [PATCH v3 2/2] phy: qcom: qmp-combo: Add SM8475 support ---
commit d1b4bfb2d91dc0cdfa3d2edd1cdd59ff8122136f
Author: Esteban Urrutia <esteuwu@proton.me>
phy: qcom: qmp-combo: Add SM8475 support
This commit adds USB/DP combo PHY support for the SM8475 SoC, introducing
specific RX and PCS USB tables while reusing existing serdes, TX, and PCS
tables. It also adds v1 PLL structures to address link training issues caused
by reference clock differences on 4nm-v1 PLLs.
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index cdcfad2e86b1d..52b07de2c52b5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
[ ... ]
> @@ -2845,6 +2965,51 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
> .has_pwrdn_delay = true,
> };
>
> +static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = {
> + .offsets = &qmp_combo_offsets_v3,
[ ... ]
> + .dp_aux_init = qmp_v4_dp_aux_init,
> + .configure_dp_tx = qmp_v4_configure_dp_tx,
> + .configure_dp_clocks = qmp_v3_configure_dp_clocks,
> + .configure_dp_phy = qmp_v4_configure_dp_phy,
> +
> + .regs = qmp_v6_usb3phy_regs_layout,
[Severity: Medium]
Is the .calibrate_dp_phy callback missing here?
Other v6 DP PHY configurations (like sm8550 and sar2130p) assign this to
qmp_v4_calibrate_dp_phy. Without the calibration callback, calls to
phy_calibrate() from the DRM driver return 0 without actually adjusting the
DP AUX tuning parameters (QSERDES_DP_PHY_AUX_CFG1).
Can this cause DP Alt Mode link training to fail on stricter sink devices or
with marginal cables that require alternative AUX calibration values?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-sm8475-bup-usbss-v3-0-0dd5da218ab2@proton.me?part=2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
prev parent reply other threads:[~2026-07-23 2:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 2:00 [PATCH v3 0/2] Initial QMP USB PHY support for SM8475 Esteban Urrutia via B4 Relay
2026-07-23 2:00 ` [PATCH v3 1/2] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY Esteban Urrutia via B4 Relay
2026-07-23 2:00 ` [PATCH v3 2/2] phy: qcom: qmp-combo: Add SM8475 support Esteban Urrutia via B4 Relay
2026-07-23 2:09 ` Esteban Urrutia
2026-07-23 2:11 ` sashiko-bot [this message]
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