From: sashiko-bot@kernel.org
To: "Qiang Yu" <qiang.yu@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,
neil.armstrong@linaro.org, olteanv@gmail.com,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy
Date: Thu, 23 Jul 2026 02:45:53 +0000 [thread overview]
Message-ID: <20260723024554.400FD1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260722-glymur_linkmode_0722-v6-5-bba8156b8cbb@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added `pcie3b_phy` node lacks the `vdda-phy-supply` and `vdda-pll-supply` properties, which will trigger `dtbs_check` errors.
--
--- Patch [5]: [PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy ---
commit 919bcfc5a66ac884962879da8e57f8559595dcdf
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>
arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy
This patch removes the unused pcie3a and shared pcie3_phy nodes from the
Mahua device tree, as it only uses PCIe3b. It replaces them with a dedicated
pcie3b_phy node using the existing Gen5x4 PHY compatible, and updates the
GCC pipe clock parent and PCIe3b port phy references accordingly.
> diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
> index 22822b6b2e8b9..3280eb96d61c0 100644
> --- a/arch/arm64/boot/dts/qcom/mahua.dtsi
> +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
[ ... ]
> @@ -134,6 +186,43 @@ &pcie_west_slv_noc {
> compatible = "qcom,mahua-pcie-west-slv-noc";
> };
>
> +&soc {
> + pcie3b_phy: phy@1b90000 {
> + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy";
> + reg = <0x0 0x01b90000 0x0 0x10000>;
[Severity: Low]
Does this node need to define vdda-phy-supply and vdda-pll-supply?
The qcom,glymur-qmp-gen5x4-pcie-phy compatible requires these properties
according to the bindings schema. Without them, this might trigger
schema validation failures during make dtbs_check.
> +
> + clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>,
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-glymur_linkmode_0722-v6-0-bba8156b8cbb@oss.qualcomm.com?part=5
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2026-07-23 2:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 2:30 [PATCH v6 0/6] Add QMP PCIe multiple link-mode PHY support Qiang Yu
2026-07-23 2:30 ` [PATCH v6 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY Qiang Yu
2026-07-23 2:33 ` sashiko-bot
2026-07-23 7:17 ` Krzysztof Kozlowski
2026-07-23 12:58 ` Manivannan Sadhasivam
2026-07-23 2:30 ` [PATCH v6 2/6] phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver Qiang Yu
2026-07-23 2:44 ` sashiko-bot
2026-07-23 7:27 ` Neil Armstrong
2026-07-23 13:19 ` Manivannan Sadhasivam
2026-07-23 2:30 ` [PATCH v6 3/6] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY Qiang Yu
2026-07-23 2:41 ` sashiko-bot
2026-07-23 13:29 ` Manivannan Sadhasivam
2026-07-23 2:30 ` [PATCH v6 4/6] arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy Qiang Yu
2026-07-23 2:30 ` [PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy Qiang Yu
2026-07-23 2:45 ` sashiko-bot [this message]
2026-07-23 2:30 ` [PATCH v6 6/6] arm64: dts: qcom: mahua-crd: Add PHY supplies for pcie3b_phy Qiang Yu
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