Re: [PATCH RESEND v3 2/2] phy: qcom: qmp-combo: Add SM8475 support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] Missing `.calibrate_dp_phy` callback assignment in the newly added `sm8475_usb3dpphy_cfg` struct.

Pre-existing issues:
- [High] SAR2130P configuration is not updated to use the new v1 DP PLL tables despite being explicitly identified as a v1 SoC.
--

--- Patch [2]: [PATCH RESEND v3 2/2] phy: qcom: qmp-combo: Add SM8475 support ---
commit 1b30757e50e17e9f7e360c8987c9aafc76411e20
Author: Esteban Urrutia <esteuwu@proton.me>

phy: qcom: qmp-combo: Add SM8475 support

This patch adds USB3 and DP combo PHY support for the Qualcomm SM8475 SoC.
It introduces new RX and PCS USB tables, reuses others from existing SoCs,
and adds specific v1 PLL structures for 4nm-v1 SoCs to fix link training
failures caused by reference clock differences.

> Some SoCs such as SAR2130P, SM7550, SM7635 and SM8475 use 4nm-v1 PLLs.
> For SM8475, trying to use qmp_v6_dp_serdes_tbl structs (which are for
> 4nm-v1.1 PLLs) causes link training to fail because of ref clock
> differences, which in turn makes these structs differ.

[Severity: High]
This is a pre-existing issue, but since this patch introduces the v1 DP PLL
tables to fix link training for 4nm-v1 PLLs, shouldn't
sar2130p_usb3dpphy_cfg also be updated to use them?

Currently sar2130p_usb3dpphy_cfg still references the incompatible v1.1
tables (qmp_v6_dp_serdes_tbl), which according to this commit message
causes link training to fail on these SoCs.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index cdcfad2e86b1d..52b07de2c52b5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

[ ... ]

> @@ -2845,6 +2965,51 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
>  	.has_pwrdn_delay	= true,
>  };
>  
> +static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = {
> +	.offsets		= &qmp_combo_offsets_v3,

[ ... ]

> +	.dp_aux_init		= qmp_v4_dp_aux_init,
> +	.configure_dp_tx	= qmp_v4_configure_dp_tx,
> +	.configure_dp_clocks	= qmp_v3_configure_dp_clocks,
> +	.configure_dp_phy	= qmp_v4_configure_dp_phy,

[Severity: High]
Is the .calibrate_dp_phy callback intentionally omitted here?

Without the calibration loop being assigned (e.g., to
qmp_v4_calibrate_dp_phy), DP link training will not iterate through
different voltage swing and pre-emphasis settings upon a failure. This
could cause link training failures with certain cables or external displays.

> +
> +	.regs			= qmp_v6_usb3phy_regs_layout,
> +	.reset_list		= msm8996_usb3phy_reset_l,
> +	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
> +	.vreg_list		= qmp_phy_vreg_l,
> +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804-sm8475-bup-usbss-v3-0-9a5b9ebf62de@proton.me?part=2

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