Re: [PATCH 4/4] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] V10 PHY fails to configure AON_TOGGLE_ENABLE because its valid register offset is 0x00.
--

commit 48ad62e543f72364fa66abb8ebcbc97d66127f66
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

This patch adds USB3+DP PHY support for the Nord SoC, which provides two
combo PHYs. It introduces a new qmp_combo_offsets_v6 structure to handle
the specific hardware layout, including a dedicated usb3_pcs_aon region at
offset 0x1e00.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index c39ced168d035..de82c7107c92e 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
[ ... ]
> @@ -5359,6 +5421,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
>  		.compatible = "qcom,hawi-qmp-usb3-dp-phy",
>  		.data = &hawi_usb3dpphy_cfg,
>  	},
> +	{
> +		.compatible = "qcom,nord-qmp-usb3-dp-phy",
> +		.data = &nord_usb3dpphy_cfg,
> +	},

[Severity: High]
This is a pre-existing issue, but I noticed a potential problem for V10
PHYs like hawi during initialization in qmp_combo_power_on().

Looking at qmp_combo_power_on():

drivers/phy/qualcomm/phy-qcom-qmp-combo.c:qmp_combo_power_on() {
	...
	/* override hardware control for reset of qmp phy */
	if (aon_toggle && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) {
		qphy_clrbits(aon_toggle, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
		qphy_clrbits(aon_toggle, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1);
	}
	...
}

For V10 PHYs, cfg->regs[QPHY_AON_TOGGLE_ENABLE] is assigned
QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE, which evaluates to 0x00. Since 0x00
evaluates to false, the condition silently skips the mandatory AON toggle
configuration.

Failing to override the hardware reset for the QMP PHY could cause the
USB3/DP PHY to fail to initialize properly on V10 platforms.

Is it intentional that a valid offset of 0x00 will cause this check to fail?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260901095055.42229-1-shengchao.guo@oss.qualcomm.com?part=4

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