Re: [PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing FIELD_PREP() for EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK causes bits 11:8 to always evaluate to 0, breaking the 48MHz PLL configuration.
--

commit 8f10cea005e7c30e78e3855b1b3db039eba68023
Author: Xu Yang <xu.yang_2@nxp.com>

phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition
    
According to Synopsys eUSB2 PHY Databook, FSEL_48_MHZ_VAL should be 0x6
for supported 48 MHz reference clock.

> diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c
> index af4fa17ac6cbc..3cb18d6ebc1d2 100644
> --- a/drivers/phy/phy-snps-eusb2.c
> +++ b/drivers/phy/phy-snps-eusb2.c
> @@ -21,7 +21,7 @@
>  #define FSEL_20_MHZ_VAL			(0x1)
>  #define FSEL_24_MHZ_VAL			(0x2)
>  #define FSEL_26_MHZ_VAL			(0x3)
> -#define FSEL_48_MHZ_VAL			(0x2)
> +#define FSEL_48_MHZ_VAL			(0x6)

[Severity: High]
This is a pre-existing issue, but does the missing FIELD_PREP() prevent the
48MHz configuration from working on Exynos devices?

When using the 48MHz reference clock, EXYNOS_DIV_11_8_48_MHZ_VAL is 0x1. 
However, in exynos_eusb2_ref_clk_init(), the PLL config is written without 
shifting:

drivers/phy/phy-snps-eusb2.c:exynos_eusb2_ref_clk_init() {
	snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1,
				    EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK,
				    config->div_11_8_val);
}

Because snps_eusb2_hsphy_write_mask() applies the mask bitwise:

drivers/phy/phy-snps-eusb2.c:snps_eusb2_hsphy_write_mask() {
	reg &= ~mask;
	reg |= val & mask;
}

Since val is 0x1 and mask is EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK (0x0F00),
the bitwise AND evaluates to 0, leaving bits 11:8 zeroed.

Should FIELD_PREP() be used here to ensure the 48MHz configuration applies
properly?

>  
>  #define EXYNOS_USB_PHY_CFG_PLLCFG0	(0x8)
>  #define PHY_CFG_PLL_FB_DIV_19_8_MASK	GENMASK(19, 8)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908085953.3315953-1-xu.yang_2@oss.nxp.com?part=1

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