From: sashiko-bot@kernel.org
To: "Nabige Aala" <nabige.aala@oss.qualcomm.com>
Cc: linux-phy@lists.infradead.org, vkoul@kernel.org,
neil.armstrong@linaro.org, olteanv@gmail.com
Subject: Re: [PATCH v4 1/9] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout
Date: Tue, 08 Sep 2026 14:30:13 +0000 [thread overview]
Message-ID: <20260908143013.EAF1D1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260908-glymur-phy-v3-v4-1-ff22e5150538@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incomplete migration to DP COM v8 macros in `qmp_v8_n3_usb43dpphy_regs_layout`.
--
commit 7145547c9c8156e9bd6b404c8a392eeca721fb95
Author: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout
Add the new DP-specific QSERDES COM v8 header file and update the
register layout to use DP-specific status register offsets for
C_READY_STATUS and CMN_STATUS registers.
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index c39ced168d035..4d31637f1dce6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
[ ... ]
> @@ -318,8 +319,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE,
>
> [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL,
[Severity: Low]
Should this also be updated to the new DP macro DP_QSERDES_V8_COM_RESETSM_CNTRL?
It looks like we're mixing USB and DP COM macros for DP Serdes configuration
registers here in qmp_v8_n3_usb43dpphy_regs_layout.
> - [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS,
> - [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS,
> + [QPHY_COM_C_READY_STATUS] = DP_QSERDES_V8_COM_C_READY_STATUS,
> + [QPHY_COM_CMN_STATUS] = DP_QSERDES_V8_COM_CMN_STATUS,
> [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
[Severity: Low]
Does QPHY_COM_BIAS_EN_CLKBUFLR_EN also need updating to
DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN to be consistent with the changes above?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com?part=1
--
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next prev parent reply other threads:[~2026-09-08 14:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 14:00 [PATCH v4 0/9] phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur Nabige Aala
2026-09-08 14:00 ` [PATCH v4 1/9] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout Nabige Aala
2026-09-08 14:30 ` sashiko-bot [this message]
2026-09-08 14:00 ` [PATCH v4 2/9] phy: qualcomm: qmp-combo: Update DP PHY common init tables Nabige Aala
2026-09-08 14:00 ` [PATCH v4 3/9] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Nabige Aala
2026-09-08 14:00 ` [PATCH v4 4/9] phy: qualcomm: qmp-combo: Add hardware-specific DP PHY config fields Nabige Aala
2026-09-08 14:16 ` sashiko-bot
2026-09-11 5:25 ` Manivannan Sadhasivam
2026-09-08 14:00 ` [PATCH v4 5/9] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur Nabige Aala
2026-09-11 5:27 ` Manivannan Sadhasivam
2026-09-08 14:00 ` [PATCH v4 6/9] phy: qualcomm: qmp-combo: Extract common DP PHY init sequence Nabige Aala
2026-09-11 5:30 ` Manivannan Sadhasivam
2026-09-11 12:25 ` Nabige Aala
2026-09-08 14:01 ` [PATCH v4 7/9] phy: qualcomm: qmp-combo: Update qmp_v8_configure_dp_clocks() for Glymur Nabige Aala
2026-09-08 14:26 ` sashiko-bot
2026-09-11 5:37 ` Manivannan Sadhasivam
2026-09-08 14:01 ` [PATCH v4 8/9] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences Nabige Aala
2026-09-11 5:38 ` Manivannan Sadhasivam
2026-09-08 14:01 ` [PATCH v4 9/9] phy: qualcomm: qmp-combo: Fix error propagation in qmp_combo_dp_power_on() Nabige Aala
2026-09-08 14:44 ` sashiko-bot
2026-09-11 5:39 ` Manivannan Sadhasivam
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