From: sashiko-bot@kernel.org
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: conor+dt@kernel.org, neil.armstrong@linaro.org,
devicetree@vger.kernel.org, olteanv@gmail.com, vkoul@kernel.org,
linux-phy@lists.infradead.org, robh@kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY
Date: Tue, 15 Sep 2026 10:18:28 +0000 [thread overview]
Message-ID: <20260915101828.D552F1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915101022.23852-2-angelogioacchino.delregno@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: strict array prevents 1-lane S-PHY nvmem configuration
--
commit c6841c20d82c1db99761e33c189c44960b8b5284
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY
This commit adds device tree bindings for the MediaTek PCI-Express Gen4 S-PHY
found in newer SoCs like the MT8196. The PHY supports link rates up to 16.0
GT/s per lane, up to two lanes, and both Root Complex and End Point modes.
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml
> new file mode 100644
> index 0000000000000..3fd1bfbc3822f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8196-pcie-sphy.yaml
[ ... ]
> + nvmem-cell-names:
> + items:
> + - const: int-r
[ ... ]
> + - const: tx-lanes-pmos
> + - const: tx-lanes-nmos
> + - const: tx-ln0-rswn
> + - const: tx-ln1-rswn
> + - const: cal-version
[Severity: Medium]
Does this rigid array structure prevent valid 1-lane S-PHY configurations from
passing schema validation?
Defining a device tree node for a 1-lane PHY typically involves omitting the
unused "tx-ln1-rswn" eFuse cell. However, because the items array enforces
strict positional constraints, omitting that entry shifts the index of the
global "cal-version" cell. This will cause dt_binding_check to fail for
legitimate 1-lane configurations.
Could the schema be adjusted to allow the second lane's eFuse cell to be
optional without breaking the expected position of "cal-version"? Otherwise,
it seems DT authors are forced to either drop calibration entirely or include
irrelevant dummy eFuse references.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260915101022.23852-1-angelogioacchino.delregno@collabora.com?part=1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2026-09-15 10:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 10:10 [PATCH v4 0/2] PHY: Add MediaTek PCI-Express Gen4 S-PHY Driver AngeloGioacchino Del Regno
2026-09-15 10:10 ` [PATCH v4 1/2] dt-bindings: phy: Document MT8196 MediaTek PCI-Express Gen4 S-PHY AngeloGioacchino Del Regno
2026-09-15 10:18 ` sashiko-bot [this message]
2026-09-15 10:58 ` AngeloGioacchino Del Regno
2026-09-15 10:10 ` [PATCH v4 2/2] phy: mediatek: Add support for " AngeloGioacchino Del Regno
2026-09-15 10:26 ` sashiko-bot
2026-09-15 10:59 ` AngeloGioacchino Del Regno
2026-10-05 10:20 ` [PATCH v4 0/2] PHY: Add MediaTek PCI-Express Gen4 S-PHY Driver Vinod Koul
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