From: sashiko-bot@kernel.org
To: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
Cc: neil.armstrong@linaro.org, linux-pci@vger.kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
Frank.Li@kernel.org, imx@lists.linux.dev, vkoul@kernel.org,
wsa+renesas@sang-engineering.com, olteanv@gmail.com,
linux-phy@lists.infradead.org, robh@kernel.org
Subject: Re: [PATCH RFC v3 12/12] arm64: dts: s32g: Add S32G3-RDB3 SerDes routing variants
Date: Sun, 20 Sep 2026 06:55:03 +0000 [thread overview]
Message-ID: <20260920065503.915DB1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260919-s32g_serdes-v3-12-9d68868c1e89@oss.nxp.com>
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The S32G3-VNP-RDB3 board wires GMAC0 to an on-board KSZ9031 RGMII PHY by
> default. Add two device tree variants that reroute GMAC0 over the
> SerDes_0 XPCS lane for SGMII, matching the two SerDes lane layouts:
>
> - Mode 1: PCIe x1 root complex on lane 0 plus 1G SGMII via GMAC0
> (XPCS0) on lane 1.
> - Mode 3: dual SGMII, GMAC0 (XPCS0) on lane 0 and PFE_EMAC_2 (XPCS1)
> on lane 1.
>
> The SerDes SUBSYS_MODE is derived from the lane child nodes present, so
> each layout requires its own board device tree. The Mode 1 variant
> enables both PCIe root complexes and extends their root ports by label
> (pcie0_rp, pcie1_rp), matching the RDB3 wiring: PCIe_0 reaches the M.2
> [ ... ]
> - Mode 1: GMAC0 SGMII path up, and both PCIe root complexes come up -
> PCIe_1 enumerates the card-slot NIC and passes traffic at full line
> rate, PCIe_0 enumerates the M.2 slot with SW17-2 ON.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com?part=12
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
prev parent reply other threads:[~2026-09-20 6:55 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-19 6:54 [PATCH RFC v3 00/12] Add support for the NXP S32G SerDes subsystem Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 01/12] dt-bindings: phy: Add " Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 02/12] dt-bindings: net: nxp,s32-dwmac: Document pcs-handle Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 04/12] net: pcs: add NXP SerDes XPCS shared core Jan Petrous via B4 Relay
2026-09-19 15:31 ` Maxime Chevallier
2026-09-19 16:31 ` Coia Prant
2026-09-20 6:54 ` sashiko-bot
2026-09-20 18:39 ` Andrew Lunn
2026-09-19 6:54 ` [PATCH RFC v3 05/12] net: pcs: Add NXP S32G XPCS driver Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-20 17:07 ` Andrew Lunn
2026-09-19 6:54 ` [PATCH RFC v3 06/12] phy: freescale: s32g: Add SerDes subsystem PHY Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 07/12] net: stmmac: dwmac-s32: Add SGMII support Jan Petrous via B4 Relay
2026-09-19 12:04 ` Maxime Chevallier
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 08/12] MAINTAINERS: Add NXP S32G SerDes and SerDes xPCS core entries Jan Petrous via B4 Relay
2026-09-19 6:54 ` [PATCH RFC v3 09/12] arm64: dts: s32g: Add SCMI reset controller Jan Petrous via B4 Relay
2026-09-20 6:54 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 10/12] arm64: dts: s32g: Add SerDes controller nodes Jan Petrous via B4 Relay
2026-09-20 6:55 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 11/12] arm64: dts: s32g: Add PCIe " Jan Petrous via B4 Relay
2026-09-20 6:55 ` sashiko-bot
2026-09-19 6:54 ` [PATCH RFC v3 12/12] arm64: dts: s32g: Add S32G3-RDB3 SerDes routing variants Jan Petrous via B4 Relay
2026-09-20 6:55 ` sashiko-bot [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260920065503.915DB1F00893@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Frank.Li@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=imx@lists.linux.dev \
--cc=jan.petrous@oss.nxp.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=neil.armstrong@linaro.org \
--cc=olteanv@gmail.com \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=vkoul@kernel.org \
--cc=wsa+renesas@sang-engineering.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox