From: sashiko-bot@kernel.org
To: "Dmitry Baryshkov" <dmitry.baryshkov@oss.qualcomm.com>
Cc: olteanv@gmail.com, vkoul@kernel.org, neil.armstrong@linaro.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH v3 3/3] phy: qcom-qusb2: describe autoresume bit
Date: Sun, 20 Sep 2026 14:12:04 +0000 [thread overview]
Message-ID: <20260920141204.EC6081F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260920-fix-qusb2-v3-3-c273e75c9fb7@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] phy: qcom-qusb2: unintended enablement of autoresume on shikra
--
commit 6cea71c32d5d262ae5774576aa04ba1bbd3cb5de
Author: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
phy: qcom-qusb2: describe autoresume bit
This patch updates the register definitions for the QUSB2 PHY autoresume bit,
specifying which register to use for autoresume handling. It defines both TEST1
and TEST_CTRL registers and merges duplicate layouts.
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index a1de05a831288..101c0820023d4 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
[ ... ]
> @@ -379,7 +375,6 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
> .se_clk_scheme_default = false,
> .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> .mask_core_ready = PLL_LOCKED,
> - .autoresume_en = BIT(3),
> };
>
> static const struct qusb2_phy_cfg shikra_phy_cfg = {
[Severity: Medium]
Does this unintentionally enable autoresume on Shikra platforms?
Previously, shikra_phy_cfg omitted .autoresume_en, meaning it defaulted
to 0. During runtime suspend, the bitwise operations in
qusb2_phy_runtime_suspend() used a 0 mask, effectively not toggling any
bits.
With this patch, omitting .autoresume_disable in shikra_phy_cfg defaults
it to false. This causes qusb2_phy_runtime_suspend() to unconditionally enter
its toggle logic and actively toggle BIT(3) at register 0xb8
(QUSB2PHY_PORT_TEST_CTRL) on Shikra.
Could this hardware state change cause undefined behavior? To preserve the
previous behavior, should .autoresume_disable = true be added to
shikra_phy_cfg?
> @@ -402,7 +397,6 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = {
> .se_clk_scheme_default = true,
> .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> .mask_core_ready = PLL_LOCKED,
> - .autoresume_en = BIT(3),
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260920-fix-qusb2-v3-0-c273e75c9fb7@oss.qualcomm.com?part=3
--
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linux-phy@lists.infradead.org
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prev parent reply other threads:[~2026-09-20 14:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-20 13:59 [PATCH v3 0/3] phy: qcom-qusb2: sort out register layouts Dmitry Baryshkov
2026-09-20 13:59 ` [PATCH v3 1/3] phy: qcom-qusb2: enable autoresume on Talos platforms Dmitry Baryshkov
2026-09-20 13:59 ` [PATCH v3 2/3] phy: qcom-qusb2: correst PHY description for IPQ6018 Dmitry Baryshkov
2026-09-20 13:59 ` [PATCH v3 3/3] phy: qcom-qusb2: describe autoresume bit Dmitry Baryshkov
2026-09-20 14:12 ` sashiko-bot [this message]
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