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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH net-next v10 04/11] dt-bindings: net: pcs: add rockchip,rk3568-xpcs support Date: Wed, 23 Sep 2026 04:03:28 +0800 Message-ID: <20260922200336.2201212-5-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260922200336.2201212-1-coiaprant@gmail.com> References: <20260922200336.2201212-1-coiaprant@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260922_130419_407714_E2D92C5D X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add device tree binding documentation for the Synopsys DesignWare XPCS integrated on the Rockchip RK3568 SoC. The XPCS is accessed over the APB3 bus and internally connected to a Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII, and QSGMII modes, with four MII ports. The four MII ports are described as ethernet-pcs-mii@N child nodes, consumed by the Rockchip XPCS glue driver later in this series. phys and phy-names are required because dtbs_check only validates required properties for enabled nodes. The SerDes link is a board-level design choice (combphy1 on some boards, combphy2 on others), so these properties must be provided by the board device tree, not the SoC dtsi. The CRU reset lines (SRST_XPCS*) are intentionally not described: no in-tree user requests them, and bring-up relies on the PD_PIPE power domain, the SerDes PHY and the in-IP soft reset. They can be added later as optional without breaking ABI. Signed-off-by: Coia Prant --- .../net/pcs/rockchip,rk3568-xpcs.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml new file mode 100644 index 0000000000000..703fcff0e3f70 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip,rk3568-xpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + + The block contains four MII ports that can be individually enabled and + routed to one of the Ethernet GMAC controllers via the pcs-handle + property in the MAC device tree node. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + items: + - description: APB3 bus interface clock (clk_csr_i), required for register access + - description: EEE clock (clk_eee_i), required for Energy Efficient Ethernet operation + + clock-names: + items: + - const: csr + - const: eee + + phys: + maxItems: 1 + + phy-names: + const: serdes + + power-domains: + maxItems: 1 + +patternProperties: + "^ethernet-pcs-mii@[0-3]$": + type: object + description: + One of the four MII ports of the XPCS. The port is linked to an + Ethernet MAC controller via the pcs-handle property in the MAC's + device tree node. + + properties: + reg: + description: MII port number. + enum: [0, 1, 2, 3] + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - phys + - phy-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + ethernet-pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + reg = <0xfda00000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + phys = <&combphy2 PHY_TYPE_SGMII>; + phy-names = "serdes"; + power-domains = <&power RK3568_PD_PIPE>; + + ethernet-pcs-mii@0 { + reg = <0>; + }; + }; -- 2.47.3 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy