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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This series adds PCIe Endpoint mode support for the Monaco (QCS8300) SoC, which has two PCIe controllers capable of operating as Endpoints. - Patch 1 documents the dedicated 16 GT/s x4 QMP PCIe PHY compatible for QCS8300, correcting an earlier gap where this PHY variant had no QCS8300-specific compatible of its own. - Patch 2 documents the QCS8300 compatible for the PCIe Endpoint controller binding, with SA8775P as its fallback. - Patch 3 adds the corresponding Endpoint PHY register configuration to the QMP PCIe PHY driver, reusing the existing SA8775P programming for the 16 GT/s x2 PHY and adding a new configuration for the 16 GT/s x4 PHY. - Patch 4 fixes clock-enable ordering in the qcom-ep controller driver: some platforms require the interconnect bandwidth vote to be set before enabling clocks, otherwise certain clocks can get stuck off. - Patch 5 fixes the existing pcie1_phy node's compatible string to list the new QCS8300-specific compatible first, ahead of the SA8775P fallback, matching the order used elsewhere in this series. - Patch 6 adds the Endpoint device tree nodes for both Monaco PCIe controllers, covering register regions, clocks, interrupts, interconnects, IOMMU mappings, resets, power domains, and PHY connections. Signed-off-by: Krishna Chaitanya Chundru --- Changes in v2: - dt-bindings: PCI: qcom-ep: Drop qcs8300 compatible from the standalone enum list(Krzysztof) - PCI: qcom-ep: Fix qcom_pcie_disable_resources() to tear down resources in strict LIFO order (phy -> clocks -> interconnect bandwidth), matching the enable path's error-unwind sequence. (Sashiko AI review) - arm64: qcom: monaco: Add reset-gpios and wake-gpios to the pcie0_ep and pcie1_ep nodes so the EP driver owns and correctly manages the PERST# and WAKE# lines; drop the output-low override from the wake-pins pinctrl state that was permanently asserting WAKE#. (Sashiko AI review) - phy: qcom: qmp-pcie: Reword commit message to clarify the new RX tuning sequence for the 16 GT/s x4 PHY is common to RC and EP modes, not EP-only. - Link to v1: https://patch.msgid.link/20260921-monaco_ep-v1-0-63c5282fb0db@oss.qualcomm.com --- Krishna Chaitanya Chundru (6): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY dt-bindings: PCI: qcom-ep: Add QCS8300 compatible phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300 PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first arm64: qcom: monaco: Add PCIe Endpoint nodes .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 4 + .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 87 ++++++------ arch/arm64/boot/dts/qcom/monaco.dtsi | 150 ++++++++++++++++++++- drivers/pci/controller/dwc/pcie-qcom-ep.c | 36 ++--- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 +++++++++++++++ 5 files changed, 322 insertions(+), 60 deletions(-) --- base-commit: 0927a1e73df63eda38bb120b91e50d746d640e17 change-id: 20260918-monaco_ep-fb14fafd0ecc Best regards, -- Krishna Chaitanya Chundru -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy