From: Agustin Santiago Isasmendi <isasmendi.agus@gmail.com>
To: Navid Ghahremani <ghahramani.navid@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
stefandoesinger@gmail.com, krzk@kernel.org,
Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 11/24] phy: zte: Add ZTE ZX279128S PCIe PHY driver
Date: Fri, 6 Nov 2026 11:13:07 +0100 [thread overview]
Message-ID: <20261106101307.3936492-2-isasmendi.agus@gmail.com> (raw)
In-Reply-To: <20261014072109.1759502-12-ghahramani.navid@gmail.com>
Hi Navid,
On Wed, Oct 14, 2026 at 08:20:51AM +0100, Navid Ghahremani wrote:
> + if (i == 0 && port->has_cal) {
> + ret = regmap_write(zphy->regmap, CRM1_PHY1_CAL1, 0x00202d5a);
> + if (ret)
> + return ret;
> + ret = regmap_write(zphy->regmap, CRM1_PHY1_CAL0, 0x0046c24a);
On my unit both read back 0 after boot: there seems to be no register
at 0x1b0/0x1b4 in the top CRM. The vendor kernel writes these two
values into the port 1 controller's "ctrl" window instead
(0x09600000 + 0x1b4, then + 0x1b0); with this series those read
0x00203c78 / 0x0c46c24a. The link trains anyway (the MT7916 enumerates
at 2.5 GT/s), so it may only matter for signal margin, but as written
the writes have no effect.
Agustin
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next prev parent reply other threads:[~2026-11-06 10:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20261014072109.1759502-1-ghahramani.navid@gmail.com>
2026-10-14 7:20 ` [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding Navid Ghahremani
2026-10-15 7:24 ` sashiko-bot
2026-10-15 9:29 ` Krzysztof Kozlowski
2026-11-13 0:37 ` Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 11/24] phy: zte: Add ZTE ZX279128S PCIe PHY driver Navid Ghahremani
2026-10-15 7:24 ` sashiko-bot
2026-11-06 10:13 ` Agustin Santiago Isasmendi [this message]
2026-11-13 0:36 ` Navid Ghahremani
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