* [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528
@ 2025-09-10 12:20 Chukun Pan
2025-09-10 12:44 ` Yao Zi
2025-09-11 8:55 ` Heiko Stübner
0 siblings, 2 replies; 3+ messages in thread
From: Chukun Pan @ 2025-09-10 12:20 UTC (permalink / raw)
To: Vinod Koul
Cc: Yao Zi, Heiko Stuebner, Kishon Vijay Abraham I, linux-arm-kernel,
linux-rockchip, linux-phy, linux-kernel, Chukun Pan
The naneng-combphy driver already has DT property checks for
"rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
the rk3528_combphy_cfg. Also aligned the indentation of the
rk3528_combphy_grfcfgs parameters (using tabs).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index a3ef19807b9e..ad6c8a11951b 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -518,7 +518,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
return -EINVAL;
}
- if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
+ if (priv->ext_refclk) {
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
@@ -543,11 +543,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->type == PHY_TYPE_PCIE) {
- if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
- rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
- RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
- }
+ if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
+ rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
+ RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
return 0;
}
@@ -571,7 +569,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
/* pipe-grf */
- .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
+ .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
};
static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
--
2.25.1
--
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528
2025-09-10 12:20 [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528 Chukun Pan
@ 2025-09-10 12:44 ` Yao Zi
2025-09-11 8:55 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: Yao Zi @ 2025-09-10 12:44 UTC (permalink / raw)
To: Chukun Pan, Vinod Koul
Cc: Heiko Stuebner, Kishon Vijay Abraham I, linux-arm-kernel,
linux-rockchip, linux-phy, linux-kernel
On Wed, Sep 10, 2025 at 08:20:00PM +0800, Chukun Pan wrote:
> The naneng-combphy driver already has DT property checks for
> "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
> the rk3528_combphy_cfg. Also aligned the indentation of the
> rk3528_combphy_grfcfgs parameters (using tabs).
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
I should have noticed this simplification. Thanks for following up,
Reviewed-by: Yao Zi <ziyao@disroot.org>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index a3ef19807b9e..ad6c8a11951b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -518,7 +518,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
> return -EINVAL;
> }
>
> - if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
> + if (priv->ext_refclk) {
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>
> if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> @@ -543,11 +543,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
> }
> }
>
> - if (priv->type == PHY_TYPE_PCIE) {
> - if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
> - rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> - RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
> - }
> + if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
> + rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> + RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
>
> return 0;
> }
> @@ -571,7 +569,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
> .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
> .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
> /* pipe-grf */
> - .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
> + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
> };
>
> static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
> --
> 2.25.1
>
--
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528
2025-09-10 12:20 [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528 Chukun Pan
2025-09-10 12:44 ` Yao Zi
@ 2025-09-11 8:55 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: Heiko Stübner @ 2025-09-11 8:55 UTC (permalink / raw)
To: Vinod Koul, Chukun Pan
Cc: Yao Zi, Kishon Vijay Abraham I, linux-arm-kernel, linux-rockchip,
linux-phy, linux-kernel, Chukun Pan
Am Mittwoch, 10. September 2025, 14:20:00 Mitteleuropäische Sommerzeit schrieb Chukun Pan:
> The naneng-combphy driver already has DT property checks for
> "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
> the rk3528_combphy_cfg. Also aligned the indentation of the
> rk3528_combphy_grfcfgs parameters (using tabs).
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index a3ef19807b9e..ad6c8a11951b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -518,7 +518,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
> return -EINVAL;
> }
>
> - if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
> + if (priv->ext_refclk) {
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>
> if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> @@ -543,11 +543,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
> }
> }
>
> - if (priv->type == PHY_TYPE_PCIE) {
> - if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
> - rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> - RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
> - }
> + if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
> + rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> + RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
>
> return 0;
> }
> @@ -571,7 +569,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
> .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
> .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
> /* pipe-grf */
> - .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
> + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
> };
>
> static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
>
--
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-09-10 12:44 ` Yao Zi
2025-09-11 8:55 ` Heiko Stübner
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