From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32DE6CD3427 for ; Sun, 10 May 2026 11:26:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3tR/NNkAL1/+Bm233aI8hFVlFxTOZmGk74V3q80EMqc=; b=BjYHqLxvasVf1y lCFAql2gOnocpAjZcG1AXFUnvahsvFmQspf+EYKjtzRxMCtHouaUgit+pkaBbNwXxg6fXWvUk9XJQ qXLs3FW2kvsl2B2LtfgJaaeMqAkamqSTcmXKW9Jc+XQ6+XiPxvtSk31Lf2Bob3X028FVUQxVh+pMf GkAheswZy8vgw4YnWBEtE9m9hDB+WnCUZDFahP17SUApUqlVVMXflPv239eoIFg9mnXuOd1KY0L1t b6AzZXHFk10YBQkqF899heviaUE3RkO6RjxnrNdWCmQIT2tqW9Xcd4fOzFmsGNcmhlh0DU421+any D0EJ8psH0VRwnrLjq0hw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wM2IL-0000000Adhj-3lYb; Sun, 10 May 2026 11:26:01 +0000 Received: from mail.cjdns.fr ([5.135.140.105]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wM2II-0000000Adgp-3Jua for linux-phy@lists.infradead.org; Sun, 10 May 2026 11:26:00 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4679A34C568; Sun, 10 May 2026 13:25:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778412351; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:content-language:in-reply-to:references; bh=gRQ3wE+0XbB0ZnErVD4CCbeoSO/yAbajOQH5pgrjJeU=; b=NPLxh7e7DtfqTISFRC0FHhQeXUZw1t80Wy2QL59P/WOE3adV0dOODZAqvkBh4cw9MclBF5 p70VP70WPbCNgBjlmTNgoomIwdkyP3nVnNPfWIQLovIiTeqkudIO6DCYj6tmmX6y5KqSp0 p5Ak9ZR086mvQ3aDvCvMUSZ9lfma0429bO5DsCrAy1QCfMmdbz0d+CleBVkqb/VefKLwwI hpv/+pnU6Kjeb2CsFLUVzoaZNYFVH05o45RZ3MGtoUdqAXQes0WNTyhvgshmhaRejRHRWe hwO5XTxcqmQhv1jVfQVNt/GOOW6N6Z8CNvJ6Y/9KTcEg+Ffezc3YzOBM32AZTg== Message-ID: <23a04af8-beec-417d-8d3f-9d587bffe953@cjdns.fr> Date: Sun, 10 May 2026 13:25:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta Subject: Re: [PATCH v2 2/2] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs. To: Vinod Koul Cc: linux-phy@lists.infradead.org, naseefkm@gmail.com, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260404184918.2184070-1-cjd@cjdns.fr> <20260404184918.2184070-3-cjd@cjdns.fr> Content-Language: en-US From: Caleb James DeLisle In-Reply-To: X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260510_042559_239493_18867130 X-CRM114-Status: GOOD ( 19.77 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 10/05/2026 13:16, Vinod Koul wrote: > On 04-04-26, 18:49, Caleb James DeLisle wrote: >> Introduce support for EcoNet PCIe PHY controllers found in EN751221 >> and EN7528 SoCs, these SoCs are not identical but are similar, each >> having one Gen1 port, and one Gen1/Gen2 port. >> >> Co-developed-by: Ahmed Naseef >> Signed-off-by: Ahmed Naseef >> [cjd@cjdns.fr: add EN751221 support and refactor for clarity] >> Signed-off-by: Caleb James DeLisle >> --- >> MAINTAINERS | 1 + >> drivers/phy/Kconfig | 12 +++ >> drivers/phy/Makefile | 1 + >> drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++ >> 4 files changed, 194 insertions(+) >> create mode 100644 drivers/phy/phy-econet-pcie.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 1b016212e4cb..b2d37c7c80af 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -9177,6 +9177,7 @@ M: Caleb James DeLisle >> L: linux-mips@vger.kernel.org >> S: Maintained >> F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml >> +F: drivers/phy/phy-econet-pcie.c >> >> ECRYPT FILE SYSTEM >> M: Tyler Hicks >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 227b9a4c612e..9aad68829d72 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -66,6 +66,18 @@ config PHY_CAN_TRANSCEIVER >> functional modes using gpios and sets the attribute max link >> rate, for CAN drivers. >> >> +config PHY_ECONET_PCIE >> + tristate "EcoNet PCIe-PHY Driver" >> + depends on ECONET || COMPILE_TEST >> + depends on OF >> + select GENERIC_PHY >> + select REGMAP_MMIO >> + help >> + Say Y here to add support for EcoNet PCIe PHY driver. >> + This driver create the basic PHY instance and provides initialize >> + callback for PCIe GEN1 and GEN2 ports. This PHY is found on >> + EcoNet SoCs including EN751221 and EN7528. >> + >> config PHY_GOOGLE_USB >> tristate "Google Tensor SoC USB PHY driver" >> select GENERIC_PHY >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> index f49d83f00a3d..42959ed383fd 100644 >> --- a/drivers/phy/Makefile >> +++ b/drivers/phy/Makefile >> @@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o >> obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o >> obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o >> obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o >> +obj-$(CONFIG_PHY_ECONET_PCIE) += phy-econet-pcie.o >> obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o >> obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o >> obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o >> diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c >> new file mode 100644 >> index 000000000000..d2c6e0c1f331 >> --- /dev/null >> +++ b/drivers/phy/phy-econet-pcie.c >> @@ -0,0 +1,180 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Author: Caleb James DeLisle >> + * Ahmed Naseef >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/* Rx detection timing for EN751221: 16*8 clock cycles */ >> +#define EN751221_RXDET_VAL 16 >> + >> +/* Rx detection timing when in power mode 3 */ >> +#define EN75_RXDET_P3_REG 0xa28 >> +#define EN75_RXDET_P3_MASK GENMASK(17, 9) >> + >> +/* Rx detection timing when in power mode 2 */ >> +#define EN75_RXDET_P2_REG 0xa2c >> +#define EN75_RXDET_P2_MASK GENMASK(8, 0) >> + >> +/* Rx impedance */ >> +#define EN75_RX_IMPEDANCE_REG 0xb2c >> +#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12) >> +enum en75_rx_impedance { >> + EN75_RX_IMPEDANCE_100_OHM = 0, >> + EN75_RX_IMPEDANCE_95_OHM = 1, >> + EN75_RX_IMPEDANCE_90_OHM = 2, >> +}; >> + >> +/* PLL Invert clock */ >> +#define EN75_PLL_PH_INV_REG 0x4a0 >> +#define EN75_PLL_PH_INV_MASK BIT(5) >> + >> +struct en75_phy_op { >> + u32 reg; >> + u32 mask; >> + u32 val; >> +}; >> + >> +struct en7528_pcie_phy { >> + struct regmap *regmap; >> + const struct en75_phy_op *data; >> +}; >> + >> +/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */ >> +static const struct en75_phy_op en7528_phy_gen1[] = { >> + { >> + .reg = EN75_PLL_PH_INV_REG, >> + .mask = EN75_PLL_PH_INV_MASK, >> + .val = 1, >> + }, >> + { /* sentinel */ } >> +}; >> + >> +/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */ >> +static const struct en75_phy_op en7528_phy_gen2[] = { >> + { >> + .reg = EN75_RX_IMPEDANCE_REG, >> + .mask = EN75_RX_IMPEDANCE_MASK, >> + .val = EN75_RX_IMPEDANCE_95_OHM, >> + }, >> + { /* sentinel */ } >> +}; >> + >> +/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */ >> +static const struct en75_phy_op en751221_phy_gen2[] = { >> + { >> + .reg = EN75_RXDET_P3_REG, >> + .mask = EN75_RXDET_P3_MASK, >> + .val = EN751221_RXDET_VAL, >> + }, >> + { >> + .reg = EN75_RXDET_P2_REG, >> + .mask = EN75_RXDET_P2_MASK, >> + .val = EN751221_RXDET_VAL, >> + }, >> + { /* sentinel */ } >> +}; >> + >> +static int en75_pcie_phy_init(struct phy *phy) >> +{ >> + struct en7528_pcie_phy *ephy = phy_get_drvdata(phy); >> + const struct en75_phy_op *data = ephy->data; >> + int i, ret; >> + u32 val; >> + >> + for (i = 0; data[i].mask || data[i].val; i++) { >> + if (i) >> + usleep_range(1000, 2000); >> + >> + val = field_prep(data[i].mask, data[i].val); > Please see: > > https://sashiko.dev/#/patchset/20260425173642.406089-1-cjd%40cjdns.fr I think this is an error in that the AI is not correctly differentiating between field_prep() which accepts a non-constant mask, and FIELD_PREP() which does not. In any case I can confirm that it does compile and work correctly on the device. On another note, I think you may be the creator of Sashiko, if so, thank you for your work - it helped me with another patch already. Thanks, Caleb -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy