Re: [PATCH v3 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes

Manivannan Sadhasivam
2025-03-24T07:41:19Z

On Tue, Mar 18, 2025 at 01:41:19PM +0400, George Moussalem wrote:
>
>
> On 3/18/25 11:17, Manivannan Sadhasivam wrote:
> > On Wed, Mar 05, 2025 at 05:41:30PM +0400, George Moussalem wrote:
> > > From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> > >
> > > From: Nitheesh Sekar <quic_nsekar@quicinc.com>
> > >
> > > Add phy and controller nodes for a 2-lane Gen2 and
> > > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> > > one global interrupt.
> > >
> > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> > > Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
> > > Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 232 +++++++++++++++++++++++++-
> > > 1 file changed, 230 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > index 8914f2ef0bc4..301a044bdf6d 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > @@ -147,6 +147,234 @@ usbphy0: phy@5b000 {
> > > status = "disabled";
> > > };
> > > + pcie1: pcie@78000 {
> > > + compatible = "qcom,pcie-ipq5018";
> > > + reg = <0x00078000 0x3000>,
> > > + <0x80000000 0xf1d>,
> > > + <0x80000f20 0xa8>,
> > > + <0x80001000 0x1000>,
> > > + <0x80100000 0x1000>;
> > > + reg-names = "parf",
> > > + "dbi",
> > > + "elbi",
> > > + "atu",
> > > + "config";
> > > + device_type = "pci";
> > > + linux,pci-domain = <0>;
> > > + bus-range = <0x00 0xff>;
> > > + num-lanes = <1>;
> > > + max-link-speed = <2>;
> >
> > Why do you want to limit link speed?
>
> This was originally sent my qcom. I've just tested with and without.
> Without limiting link speed, the phy doesn't come up:
>
> [ 0.112017] qcom-pcie a0000000.pcie: host bridge /soc@0/pcie@a0000000
> ranges:
> [ 0.112116] qcom-pcie a0000000.pcie: IO 0x00a0200000..0x00a02fffff
> -> 0x00a0200000
> [ 0.112161] qcom-pcie a0000000.pcie: MEM 0x00a0300000..0x00b02fffff
> -> 0x00a0300000
> [ 0.238623] qcom-pcie a0000000.pcie: iATU: unroll T, 8 ob, 8 ib, align
> 4K, limit 1024G
> ...
> [ 1.257290] qcom-pcie a0000000.pcie: Phy link never came up
>

Wow. This should never happen unless the PHY sequences are messed up. If there
are stability issues with Gen 3, we should get runtime AER errors and the link
should atleast come up (based on experience with similar issues on other
platforms).

Sricharan/Nitheesh, may I know what is the issue here?

> >
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > +
> > > + phys = <&pcie1_phy>;
> > > + phy-names ="pciephy";
> > > +
> > > + ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */
> > > + <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */
> >
> > These ranges are wrong. Please check with other DT files.
> >
>
> Thanks, have corrected them as part of next version:
>
> ranges = <0x01000000 0 0x80200000 0x80200000 0 0x00100000>,
> <0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
>
> > Same comments to other instance as well.
>
> and:
>
> ranges = <0x01000000 0 0xa0200000 0xa0200000 0 0x00100000>,
> <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
>

LGTM.

- Mani

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