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Mon, 05 Dec 2022 13:51:46 -0800 (PST) Date: Tue, 06 Dec 2022 00:51:42 +0300 From: Dmitry Baryshkov To: Manivannan Sadhasivam , martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org CC: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v4_04/23=5D_phy=3A_qcom-qmp-ufs=3A_Add_s?= =?US-ASCII?Q?upport_for_configuring_PHY_in_HS_Series_B_mode?= User-Agent: K-9 Mail for Android In-Reply-To: <20221201174328.870152-5-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> <20221201174328.870152-5-manivannan.sadhasivam@linaro.org> Message-ID: <32201EF1-8169-4940-99E1-31CC0C37C522@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221205_135149_498015_0A4AE1D0 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 1 December 2022 20:43:09 GMT+03:00, Manivannan Sadhasivam wrote: >Add separate tables_hs_b instance to allow the PHY driver to configure the >PHY in HS Series B mode. The individual SoC configs need to supply the >serdes register setting in tables_hs_b and the UFS driver can request the >Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. > >Reviewed-by: Dmitry Baryshkov >Signed-off-by: Manivannan Sadhasivam >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >index 516027e356f0..2d5dd336aeb2 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >@@ -547,6 +547,8 @@ struct qmp_phy_cfg { > > /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ > const struct qmp_phy_cfg_tbls tbls; >+ /* Additional sequence for HS Series B */ >+ const struct qmp_phy_cfg_tbls tbls_hs_b; > > /* clock ids to be requested */ > const char * const *clk_list; >@@ -580,6 +582,7 @@ struct qmp_ufs { > struct reset_control *ufs_reset; > > struct phy *phy; >+ u32 mode; > }; > > static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) >@@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) > { > qmp_ufs_serdes_init(qmp, &cfg->tbls); >+ if (qmp->mode == PHY_MODE_UFS_HS_B) >+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); I still think that qmp_ufs_init_registers() is a way to go here , see the pcie driver. > qmp_ufs_lanes_init(qmp, &cfg->tbls); > qmp_ufs_pcs_init(qmp, &cfg->tbls); > } >@@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy) > return qmp_ufs_exit(phy); > } > >+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) >+{ >+ struct qmp_ufs *qmp = phy_get_drvdata(phy); >+ >+ qmp->mode = mode; >+ >+ return 0; >+} >+ > static const struct phy_ops qcom_qmp_ufs_phy_ops = { > .power_on = qmp_ufs_enable, > .power_off = qmp_ufs_disable, >+ .set_mode = qmp_ufs_set_mode, > .owner = THIS_MODULE, > }; > -- With best wishes Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy