From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Abel Vesa <abel.vesa@oss.qualcomm.com>,
Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Nitin Rawat <nitin.rawat@oss.qualcomm.com>
Subject: Re: [PATCH] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4
Date: Thu, 19 Feb 2026 14:34:57 +0100 [thread overview]
Message-ID: <3ee0a0b8-7070-4317-b8fb-20cb7ab467c0@oss.qualcomm.com> (raw)
In-Reply-To: <20260219-phy-qcom-qmp-ufs-fix-sm8650-pcs-g4-table-v1-1-f136505b57f6@oss.qualcomm.com>
On 2/19/26 12:11 PM, Abel Vesa wrote:
> According to internal documentation, on SM8650, when the PHY is configured
> in Gear 4, the QPHY_V6_PCS_UFS_PLL_CNTL register needs to have the same
> value as for Gear 5.
>
> At the moment, there is no board that comes with a UFS 3.x device, so
> this issue doesn't show up, but with the new Eliza SoC, which uses the
> same init sequence as SM8650, on the MTP board, the link startup fails
> with the current Gear 4 PCS table.
>
> So fix that by moving the entry into the PCS generic table instead,
> while keeping the value from Gear 5 configuration.
>
> Cc: stable@vger.kernel.org # v6.10
> Fixes: b9251e64a96f ("phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5")
> Suggested-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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next prev parent reply other threads:[~2026-02-19 13:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-19 11:11 [PATCH] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4 Abel Vesa
2026-02-19 13:34 ` Konrad Dybcio [this message]
2026-02-20 8:30 ` Neil Armstrong
2026-02-27 15:25 ` Vinod Koul
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