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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5268472ejg.26.2022.06.06.03.14.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jun 2022 03:14:21 -0700 (PDT) Message-ID: <45aa26be-625e-47eb-c21f-92497e60b6dd@linaro.org> Date: Mon, 6 Jun 2022 12:14:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Content-Language: en-US To: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" Cc: "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" , Moon-Ki Jun , Sang Min Kim , Dongjin Yang References: <20220603015431epcms2p6203908cebe6a320854136559a32b54cb@epcms2p6> <20220603023158epcms2p6949f6cd93926b9e811e1b4d52fbef91b@epcms2p6> From: Krzysztof Kozlowski In-Reply-To: <20220603023158epcms2p6949f6cd93926b9e811e1b4d52fbef91b@epcms2p6> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220606_031423_309293_6B65EA7B X-CRM114-Status: GOOD ( 16.44 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 03/06/2022 04:31, Wangseok Lee wrote: > Add description to support Axis, ARTPEC-8 SoC. > ARTPEC-8 is the SoC platform of Axis Communications > and PCIe phy is designed based on SAMSUNG PHY. This does not look like wrapped in Linux commit style. https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586 > > changes since v1 : > -'make dt_binding_check' result improvement > -Add the missing property list > -Align the indentation of continued lines/entries > > Signed-off-by: Wangseok Lee > --- > .../bindings/phy/axis,artpec8-pcie-phy.yaml | 70 ++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > new file mode 100644 > index 0000000..ab9766f > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings Same comment as patch #1. > + > +maintainers: > + - Jesper Nilsson > + > +properties: > + compatible: > + const: axis,artpec8-pcie-phy > + > + reg: > + items: > + - description: PHY registers. > + - description: PHY coding sublayer registers. > + > + reg-names: > + items: > + - const: phy > + - const: pcs > + > + "#phy-cells": > + const: 0 > + > + clocks: > + items: > + - description: PCIe PHY reference clock > + > + clock-names: > + items: > + - const: ref_clk Same comment as patch #1. > + > + num-lanes: > + const: 2 > + > +required: > + - compatible > + - reg > + - reg-names > + - "#phy-cells" > + - clocks > + - clock-names > + - num-lanes > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + artpec8 { Same comment as patch #1. > + #address-cells = <2>; > + #size-cells = <2>; > + pcie_phy: pcie-phy@16c80000 { > + compatible = "axis,artpec8-pcie-phy"; > + reg = <0x0 0x16c80000 0x0 0x2000>, > + <0x0 0x16c90000 0x0 0x1000>; > + reg-names = "phy", "pcs"; > + #phy-cells = <0>; > + clocks = <&clock_cmu_fsys 53>; > + clock-names = "ref_clk"; > + num-lanes = <2>; > + }; > + }; > +... Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy