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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id qw2-20020a0568706f0200b002397a883e7csm5033024oab.12.2024.05.01.08.37.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 May 2024 08:37:22 -0700 (PDT) Message-ID: <47665254-fe22-4369-8b10-087ca928e97f@gmail.com> Date: Wed, 1 May 2024 10:37:20 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 RESEND 0/8] ipq9574: Enable PCI-Express support To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org References: <20240501042847.1545145-1-mr.nuke.me@gmail.com> Content-Language: en-US From: mr.nuke.me@gmail.com In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240501_083726_670457_D9ECF0D3 X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 5/1/24 5:22 AM, Krzysztof Kozlowski wrote: > On 01/05/2024 06:28, Alexandru Gagniuc wrote: >> There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series >> addresses pcie2, which is a gen3x2 port. The board I have only uses >> pcie2, and that's the only one enabled in this series. pcie3 is added >> as a special request, but is untested. >> >> I believe this makes sense as a monolithic series, as the individual >> pieces are not that useful by themselves. >> >> In v2, I've had some issues regarding the dt schema checks. For >> transparency, I used the following test invocations to test: >> >> make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml >> make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml >> >> Changes since v3: >> - "const"ify .hw.init fields for the PCIE pipe clocks >> - Used pciephy_v5_regs_layout instead of v4 in phy-qcom-qmp-pcie.c >> - Included Manivannan's patch for qcom-pcie.c clocks >> - Dropped redundant comments in "ranges" and "interrupt-map" of pcie2. >> - Added pcie3 and pcie3_phy dts nodes >> - Moved snoc and anoc clocks to PCIe controller from PHY >> > > Three postings within short time... Allow people to actually review your > code. Please wait 24h before posting new version. Include entire > feedback and all tags. Explain why you ignore/skip some tags. > I'm sorry for the confusion. It's the same patch version, v3 being two weeks old. Due to a tooling failure, the first attempt to send resulted in a double-posting, and missing cover letter. It was so bad that I felt I needed to re-post with the RESEND tag to clarify the intent and prevent further confusion. Alex > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy