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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" X-Spam-Status: No, score=-5.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 9/8/26 11:40 AM, George Moussalem via B4 Relay wrote: > Patch series adds Qualcomm 22ull Super-Speed USB UNIPHY driver support > present in Qualcomm IPQ5018 and IPQ5332 SoC which is required to enable > USB3. This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe. > Either one of the interface can use it via the mux selection present in > the TCSR register. Current patch series adds the support for UNIPHY with > DWC3 USB. > > The series is now split into 3 parts: > 1. Flatten USB Controller Nodes on IPQ SoCs > link: https://lore.kernel.org/r/20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com > 2. Enable USB3 for Qualcomm IPQ5018 (this patch series) > 3. Enable USB3 for Qualcomm IPQ5332 (to be submitted) > > --- > Changes in v4: [...] > - It's worth noting that I left the logic to register 1 phy in this > patch unchanged despite Konard's suggestion to register both > (PCIe and USB3) to avoid changing the existing binding for the > existing PCIe phy instances in ipq5018/ipq5332. Although the silicon > is capable of supporting both PCIe and USB3, the instances in scope > are wired for single mode only. The next patch set will register both > PCIe and USB3 PHYs for the combo PHY instance in IPQ5332 and use > #phy-cells to select the right PHY in the respective PCIe and USB3 > controller nodes. We need a bindings change either way, so might as well do it "right"! Konrad -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy