From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>,
Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible
Date: Tue, 16 Jun 2026 16:03:39 +0200 [thread overview]
Message-ID: <5dffdbe0-cbb9-429e-ba15-0afdf6f20fba@oss.qualcomm.com> (raw)
In-Reply-To: <20260518-link_mode_0519-v4-1-269cd73cc5d1@oss.qualcomm.com>
On 5/19/26 7:47 AM, Qiang Yu wrote:
> The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the
> PCIe3a/PCIe3b controllers. This block supports two link modes:
>
> 1. x4+x4: two 4-lane PHY instances are exposed
> 2. x8: one 8-lane PHY instance is exposed
>
> Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and
> document the new link-mode property, which selects the active link mode
> via a TCSR syscon register.
>
> Document the required clocks, resets, and power-domains for both PHY
> instances active in x8 mode. Use #phy-cells = <1> for this compatible,
> where the cell value is the PHY index within the active link mode.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
[...]
> @@ -68,20 +69,29 @@ properties:
> - const: ref
> - enum: [rchng, refgen]
> - const: pipe
> - - const: pipediv2
> + - enum: [pipediv2, phy_b_aux]
I'm surprised to learn 3A doesnm'doesn't have a PIPE_DIV2 clk.. it does have
a non-div2 one though.
Seems like it's specifically not the case on Hamoa and Makena, so perhaps
it's better for maintainability if the Glymur list was separate
Konrad
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next prev parent reply other threads:[~2026-06-16 14:03 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 5:47 [PATCH RFC v4 0/9] phy: qcom: qmp-pcie: Add link-mode based support for Glymur Gen5x8 PHY Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible Qiang Yu
2026-06-16 14:03 ` Konrad Dybcio [this message]
2026-05-19 5:47 ` [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros Qiang Yu
2026-06-16 14:07 ` Konrad Dybcio
2026-05-19 5:47 ` [PATCH RFC v4 3/9] phy: qcom: qmp-pcie: Add multiple power-domains support Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 4/9] phy: qcom: qmp-pcie: Support multiple nocsr resets Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers Qiang Yu
2026-05-20 16:25 ` Dmitry Baryshkov
2026-05-22 10:57 ` Manivannan Sadhasivam
2026-05-28 13:15 ` Qiang Yu
2026-05-28 13:48 ` Dmitry Baryshkov
2026-05-29 7:02 ` Qiang Yu
2026-06-16 14:05 ` Konrad Dybcio
2026-05-19 5:47 ` [PATCH RFC v4 6/9] phy: qcom: qmp-pcie: Add clock and reset lists for secondary PHY selector Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 7/9] phy: qcom: qmp-pcie: Add link-mode multi-PHY probe infrastructure Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 8/9] phy: qcom: qmp-pcie: Add Glymur Gen5x8 PHY config and match data Qiang Yu
2026-05-19 5:47 ` [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY Qiang Yu
2026-06-17 11:19 ` Konrad Dybcio
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