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Mon, 14 Oct 2024 13:10:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49EDA13a022102 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Oct 2024 13:10:01 GMT Received: from [10.253.10.174] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 14 Oct 2024 06:09:55 -0700 Message-ID: <62785e7d-86ea-4841-ae76-4afdd612dca4@quicinc.com> Date: Mon, 14 Oct 2024 21:09:51 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt To: Krzysztof Kozlowski , Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , , , , , , References: <20241011104142.1181773-1-quic_qianyu@quicinc.com> <20241011104142.1181773-4-quic_qianyu@quicinc.com> <4802B12B-BAC1-4E99-BDFE-A2340F4A8F24@linaro.org> <3d1d0822-da66-44c8-a328-69804210123c@kernel.org> <65B34B14-76C3-491D-8A58-6D0887889018@linaro.org> <96816abb-4e0d-4c60-8ae6-b5a5cd796e99@quicinc.com> Content-Language: en-US From: Qiang Yu In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LNbswjoW0-pCJSDR8VSslzRLqzMEjKQF X-Proofpoint-ORIG-GUID: LNbswjoW0-pCJSDR8VSslzRLqzMEjKQF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 malwarescore=0 mlxlogscore=704 priorityscore=1501 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410140095 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241014_141314_236594_3E4B98BC X-CRM114-Status: GOOD ( 16.04 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 10/14/2024 4:25 PM, Krzysztof Kozlowski wrote: > On 14/10/2024 09:50, Qiang Yu wrote: >> On 10/12/2024 12:06 AM, Krzysztof Kozlowski wrote: >>> On 11/10/2024 17:51, Manivannan Sadhasivam wrote: >>>> On October 11, 2024 9:14:31 PM GMT+05:30, Krzysztof Kozlowski wrote: >>>>> On 11/10/2024 17:42, Manivannan Sadhasivam wrote: >>>>>> On October 11, 2024 8:03:58 PM GMT+05:30, Krzysztof Kozlowski wrote: >>>>>>> On Fri, Oct 11, 2024 at 03:41:37AM -0700, Qiang Yu wrote: >>>>>>>> Document 'global' SPI interrupt along with the existing MSI interrupts so >>>>>>>> that QCOM PCIe RC driver can make use of it to get events such as PCIe >>>>>>>> link specific events, safety events, etc. >>>>>>> Describe the hardware, not what the driver will do. >>>>>>> >>>>>>>> Though adding a new interrupt will break the ABI, it is required to >>>>>>>> accurately describe the hardware. >>>>>>> That's poor reason. Hardware was described and missing optional piece >>>>>>> (because according to your description above everything was working >>>>>>> fine) is not needed to break ABI. >>>>>>> >>>>>> Hardware was described but not completely. 'global' IRQ let's the controller driver to handle PCIe link specific events like Link up, Link down etc... They improve user experience like the driver can use those interrupts to start bus enumeration on its own. So breaking the ABI for good in this case. >>>>>> >>>>>>> Sorry, if your driver changes the ABI for this poor reason. >>>>>>> >>>>>> Is the above reasoning sufficient? >>>>> I tried to look for corresponding driver change, but could not, so maybe >>>>> there is no ABI break in the first place. >>>> Here it is: >>>> >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4581403f67929d02c197cb187c4e1e811c9e762a >>>> >>>> Above explanation is good, but >>>>> still feels like improvement and device could work without global clock. >>> So there is no ABI break in the first place... Commit is misleading. >> OK, will remove the description about ABI break in commit message. But may > Describe real effects. You got comments about ABI impact before, right? > So if you remove this, how previous feedback is addressed? Global interrupt is parsed as optional in driver, so there is no ABI break, will write this in commit message. Thanks Qiang > > >> I know in which case ABI will be broken by adding an interrupt in bingdings >> and what ABI will be broken? > Users of ABI stop working. > > Best regards, > Krzysztof > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy