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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id n4-20020aca2404000000b003c60db822e7sm1774266oic.4.2024.04.15.14.25.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Apr 2024 14:25:49 -0700 (PDT) Message-ID: <6726fa2b-f5fe-10fb-6aab-f76d61f0b3cd@gmail.com> Date: Mon, 15 Apr 2024 16:25:48 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY Content-Language: en-US To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org References: <20240415182052.374494-1-mr.nuke.me@gmail.com> <20240415182052.374494-7-mr.nuke.me@gmail.com> From: mr.nuke.me@gmail.com In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240415_142551_241953_5FC39018 X-CRM114-Status: GOOD ( 20.63 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 4/15/24 15:10, Dmitry Baryshkov wrote: > On Mon, 15 Apr 2024 at 21:23, Alexandru Gagniuc wrote: >> >> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream >> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others >> being reused from IPQ8074 and IPQ6018 PHYs. >> >> Signed-off-by: Alexandru Gagniuc >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- >> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ >> 2 files changed, 149 insertions(+), 1 deletion(-) >> > > [skipped] > >> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) >> >> /* list of clocks required by phy */ >> static const char * const qmp_pciephy_clk_l[] = { >> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", >> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" > > Are the NoC clocks really necessary to drive the PHY? I think they are > usually connected to the controllers, not the PHYs. The system will hang if these clocks are not enabled. They are also attached to the PHY in the QCA 5.4 downstream kernel. >> }; >> >> /* list of regulators */ >> @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { >> .rx = 0x0400, >> }; >> >> +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { >> + .serdes = 0, >> + .pcs = 0x1000, >> + .pcs_misc = 0x1400, >> + .tx = 0x0200, >> + .rx = 0x0400, >> + .tx2 = 0x0600, >> + .rx2 = 0x0800, >> +}; >> + >> static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { >> .serdes = 0, >> .pcs = 0x0a00, >> @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { >> .phy_status = PHYSTATUS, >> }; >> >> +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = { >> + .lanes = 2, >> + >> + .offsets = &qmp_pcie_offsets_ipq9574, >> + >> + .tbls = { >> + .serdes = ipq9574_gen3x2_pcie_serdes_tbl, >> + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), >> + .tx = ipq8074_pcie_gen3_tx_tbl, >> + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), >> + .rx = ipq6018_pcie_rx_tbl, >> + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), >> + .pcs = ipq6018_pcie_pcs_tbl, >> + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), >> + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, >> + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), >> + }, >> + .reset_list = ipq8074_pciephy_reset_l, >> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), >> + .vreg_list = NULL, >> + .num_vregs = 0, >> + .regs = pciephy_v4_regs_layout, > > So, is it v4 or v5? Please give me a day or so to go over my notes and give you a more coherent explanation of why this versioning was chosen. I am only working from the QCA 5.4 downstream sources. I don't have any documentation for the silicon Alex > >> + >> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, >> + .phy_status = PHYSTATUS, >> +}; >> + >> static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { >> .lanes = 2, >> > > > > -- > With best wishes > Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy