Re: [PATCH v6 4/4] phy: airoha: Add support for Airoha AN7581 USB PHY

From: Christian Marangi <ansuelsmth@gmail.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Lorenzo Bianconi <lorenzo@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 4/4] phy: airoha: Add support for Airoha AN7581 USB PHY
Date: Sat, 7 Mar 2026 11:57:40 +0100	[thread overview]
Message-ID: <69ac04a6.5d0a0220.2969f9.9d81@mx.google.com> (raw)
In-Reply-To: <52123051-0d2d-42b2-b677-99a5de0f2c4e@kernel.org>

On Sat, Mar 07, 2026 at 11:40:48AM +0100, Krzysztof Kozlowski wrote:
> On 07/03/2026 11:37, Christian Marangi wrote:
> >>> +
> >>> +		if (phy_type == PHY_TYPE_USB3) {
> >>> +			ret = of_property_read_u32(dev->of_node, "airoha,usb3-serdes",
> >>> +						   &priv->serdes_port);
> >>> +			if (ret)
> >>> +				return dev_err_probe(dev, ret, "missing serdes line for USB 3.0\n");
> >>> +
> >>> +			priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
> >>
> >> Nope, you need phandle to express proper device links.
> >>
> >> Don't sprinkle compatible lookups for new code which does not need to
> >> keep things backwards compatible. How do you manage device links
> >> without phandle? How do you manage device probe ordering?
> >>
> > 
> > Hi,
> > 
> > the phandle to SCU was present in old implementation but later dropped as it was
> > said that it wouldn't describe the HW.
> 
> 
> I went through v3 review and I did not find such said arguments. Can you
> point me to it?
> 
>

Here was v2 [0] that was clock + USB PHY. (there were clock stuff as the SCU
implementation was different) The link wasn't added in the changelog as it's
quite different than this current series.

In patch 7 Rob pointed out that serdes-port + scu was a bit unusual.

Then the implementation changed in favor of a more simple one where it's the PHY
that configure everything and in this new version the usage of the SCU phandle
is really to just get the regmap and modify the single bit to select the PHY
path/mode for USB 3.0. (it's mainly the reason the SCU is referenced directly
with a compatible instead of a phandle, in the previous implementation we used a
function exposed by the SCU SSR, while in this it's just a regmap that can
PROBE_DEFER)

Rob suggested an additional layer (a PHY) to handle this but I don't feel it
would actually describe the HW this way as that bit doesn't modify another PHY
but it just toggle the mode to the related USB 3.0 PHY.

This is really another case of not-so-organized register mapping on the SoC.

[0] https://lore.kernel.org/all/20250320130054.4804-1-ansuelsmth@gmail.com/

> > 
> > I will readd as airoha,scu. Is it ok for you?
> > 
> > (I actually prefer phandle than hardcoding compatible as it makes things more
> > descriptive and prevent all kind of problem in the future, so I'm more than
> > happy than using that)
> > 
> 
> 
> Best regards,
> Krzysztof

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