From: Neil Armstrong <neil.armstrong@linaro.org>
To: Shawn Lin <shawn.lin@rock-chips.com>, Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support
Date: Tue, 18 Nov 2025 10:12:48 +0100 [thread overview]
Message-ID: <70a23bf8-6648-489e-908f-d7727f5cccd3@linaro.org> (raw)
In-Reply-To: <1763004478-218446-1-git-send-email-shawn.lin@rock-chips.com>
On 11/13/25 04:27, Shawn Lin wrote:
> Need to control the delay PLL turnoff time if PCIe works on
> L1 PM substates.
Can you elaborate ?
>
> Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index af9a5c7..5b6f80e 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -106,6 +106,10 @@
> #define RK3568_PHYREG18 0x44
> #define RK3568_PHYREG18_PLL_LOOP 0x32
>
> +#define RK3568_PHYREG30 0x74
> +#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
> +#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
> +
> #define RK3568_PHYREG32 0x7C
> #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
> #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
> @@ -665,6 +669,11 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
> case REF_CLOCK_100MHz:
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> if (priv->type == PHY_TYPE_PCIE) {
> + /* Gate_tx_pck_sel length select for L1ss support */
> + rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
> + RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
> + RK3568_PHYREG30);
> +
> /* PLL KVCO tuning fine */
> val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> RK3568_PHYREG33_PLL_KVCO_VALUE);
Please use proper patch versioning when sending a new version, with a proper
changelog.
Neil
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next prev parent reply other threads:[~2025-11-18 9:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-13 3:27 [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support Shawn Lin
2025-11-18 9:12 ` Neil Armstrong [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-11-13 3:00 Shawn Lin
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