* [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support
@ 2025-11-13 3:27 Shawn Lin
2025-11-18 9:12 ` Neil Armstrong
0 siblings, 1 reply; 3+ messages in thread
From: Shawn Lin @ 2025-11-13 3:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, Heiko Stuebner, linux-phy, linux-rockchip,
Shawn Lin
Need to control the delay PLL turnoff time if PCIe works on
L1 PM substates.
Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index af9a5c7..5b6f80e 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -106,6 +106,10 @@
#define RK3568_PHYREG18 0x44
#define RK3568_PHYREG18_PLL_LOOP 0x32
+#define RK3568_PHYREG30 0x74
+#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
+#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
+
#define RK3568_PHYREG32 0x7C
#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
@@ -665,6 +669,11 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
+ RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
+ RK3568_PHYREG30);
+
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
RK3568_PHYREG33_PLL_KVCO_VALUE);
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support
2025-11-13 3:27 [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support Shawn Lin
@ 2025-11-18 9:12 ` Neil Armstrong
0 siblings, 0 replies; 3+ messages in thread
From: Neil Armstrong @ 2025-11-18 9:12 UTC (permalink / raw)
To: Shawn Lin, Vinod Koul
Cc: Kishon Vijay Abraham I, Heiko Stuebner, linux-phy, linux-rockchip
On 11/13/25 04:27, Shawn Lin wrote:
> Need to control the delay PLL turnoff time if PCIe works on
> L1 PM substates.
Can you elaborate ?
>
> Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index af9a5c7..5b6f80e 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -106,6 +106,10 @@
> #define RK3568_PHYREG18 0x44
> #define RK3568_PHYREG18_PLL_LOOP 0x32
>
> +#define RK3568_PHYREG30 0x74
> +#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
> +#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
> +
> #define RK3568_PHYREG32 0x7C
> #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
> #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
> @@ -665,6 +669,11 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
> case REF_CLOCK_100MHz:
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> if (priv->type == PHY_TYPE_PCIE) {
> + /* Gate_tx_pck_sel length select for L1ss support */
> + rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
> + RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
> + RK3568_PHYREG30);
> +
> /* PLL KVCO tuning fine */
> val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> RK3568_PHYREG33_PLL_KVCO_VALUE);
Please use proper patch versioning when sending a new version, with a proper
changelog.
Neil
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support
@ 2025-11-13 3:00 Shawn Lin
0 siblings, 0 replies; 3+ messages in thread
From: Shawn Lin @ 2025-11-13 3:00 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, Heiko Stuebner, Yao Zi, linux-phy,
linux-rockchip, Shawn Lin
Need to control the delay PLL turnoff time if PCIe works on
L1 PM substates.
Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index a3ef198..af9a5c7 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -21,6 +21,9 @@
#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
/* RK3528 COMBO PHY REG */
+#define RK3528_PHYREG5 0x14
+#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
+#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
#define RK3528_PHYREG6 0x18
#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
@@ -504,6 +507,11 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
+ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF,
+ RK3528_PHYREG5);
+
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
--
2.7.4
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