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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 10/7/2026 9:17 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 08:15:39PM +0530, Pradeep Pragallapati wrote: >> >> >> On 10/7/2026 7:13 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 07, 2026 at 05:03:02PM +0530, Pradeep Pragallapati wrote: >>>> >>>> >>>> On 10/7/2026 1:18 PM, Dmitry Baryshkov wrote: >>>>> On Wed, Oct 07, 2026 at 11:59:38AM +0530, Pradeep P V K wrote: >>>>>> Add the init sequence tables and config for the UFS QMP phy found in >>>>>> the Glymur SoC. >>>>>> >>>>>> Reviewed-by: Abel Vesa >>>>>> Acked-by: Konrad Dybcio >>>>>> Signed-off-by: Pradeep P V K >>>>>> --- >>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++ >>>>>> 1 file changed, 99 insertions(+) >>>>>> >>>>>> + .offsets = &qmp_ufs_offsets_v6, >>>>> >>>>> So, is it a PHY using v6 offsets, but v7 registers inside? >>>>> >>>> The QSERDES RX0 register offsets on Glymur SoC are aligned with the v7 register layout offsets. >>>> Therefore, the v7 QSERDES RX0 register offsets are used for Glymur (similar to SM8750). >>> >>> Mention in the commit message, please. >> sure, i will mention it.> >>>> >>>>>> + .max_supported_gear = UFS_HS_G5, >>>>>> + >>>>>> + .vreg_list = glymur_ufsphy_vreg_l, >>>>>> + .num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l), >>>>>> + .regs = ufsphy_v6_regs_layout, >>>>> >>>>> v7 >>> >>> This still holds. >>> >> Do you mean changing ufsphy_v6_regs_layout to ufsphy_v7_regs_layout? >> If so, no. ufsphy_v6_regs_layout contains the PCS register offsets, and the >> PCS register offsets on Glymur are aligned with ufsphy_v6_regs_layout, similar to SM8750. > > => commit message, please. > sure, i will update the commit message in my next patch series. -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy